From OLPC

These are the changes planned for the XO-4 B1 prototype, from the A2 prototypes. The list of changes made to the A2 prototypes as part of testing is the XO-4 A2 ECO list.

[edit] A2 Electrical Fixes

These changes fix problems in the A2 prototypes:

[edit] MMP3 B0B revision

[edit] Fixing +3.3V_SOC

This fixes a problem where +3.3V_SOC doesn't quite turn on.

• Change PR79 to a 10K resistor

Larger issue is that we used bipolar transistors in three places where we should have used MOSFETs. I propose changing PQ1, PQ34, and PQ42 to NMOS FETs and restoring PR40, PR79, and PR114 to 330K.

[edit] Fixing EC Programming by the SOC

This fixes the inability of the SOC to reprogram the EC.

• Add a 3K pullup resistor to +3.3V_NAND to EC_EDI_DO

[edit] New VCore

This changes to lower Vcore values for debugging and normal operation (1.3 and 1.24V), as well as a higher suspend voltage (1.0V) as suggested by Marvell for B0 silicon.

• PR62 (or PR57) should be 12.0K
• PR67 should be 18.0K
• PR66 should be 120K
• PR73 should be 30.0K

[edit] Pulse JTAG Reset at start of day

Marvell added a requirement to assert JTAG reset only at the start of day.

• Add a small schottky diode (D20) between EN_+1.35V_DDR3 and PRI_TRST#. The cathode of the diode should be connected to EN_+1.35V_DDR3.
• Remove the 100K resistor from R335.
• Populate R334 with a 100K resistor.

[edit] Changing to a +1.8V SPI Flash

Until we get the voltage translator working at SPI Flash speeds, we are disabling it and using a +1.8V 1 MByte SPI Flash ROM for U17.

• Depopulate R280 (0 ohm)
• Populate R281 with a 0 ohm resistor
• Populate R246 with a 120K resistor
• Replace U17 with a +1.8V SPI Flash
• Short Q27, pins 1 and 3
• Short Q28, pins 1 and 3
• Short Q29, pins 1 and 3
• Short D4, pins 1 and 2

[edit] Fixing SOC/EC Communications

This removes much of the voltage translation circuitry which was added to support an eventual change of masters in the EC/SOC SDI (SPI) bus. It fixes a reliability problem when talking to the EC.

• Remove the resistors from the following locations: R94 (3K), R98 (3K), R253 (3K), R258 (3K), R372 (1.2K), R373 (1.2K), and R375 (1.2K).
• Replace D18 with a 3K resistor.
• Remove Q38, and place a 3K resistor between pins 1 and 3
• Remove Q36, and place a 3K resistor between pins 1 and 3
• Add a 3K pullup resistor to +3.3VSUS_EC (or +3.3VSUS) to EC_SDI_MISO (Q37, pin 3).
• Add a 3.6K pulldown from SDI_MOSI (D18 anode) to GND
• Add a 3.6K pulldown from SDI_CLK (Q36.1) to GND
• Add a 3.6K pulldown from SDI_CS# (Q38.1) to GND

[edit] Simplify +1.2V Power

This eliminates an unnecessary power switch in the +1.2V rail (used mainly to bias some unused functional blocks in the SoC).

• Remove PQ38, PC104 and PR87
• Tie PQ38.2 to EN_NAND_SOCGPIO# and eliminate the EN_+1.2V signal from the EC.

[edit] Minor Fixes

Minor fixes suggested by Marvell upon schematic review:

• Pull JTAG_SEL high by default

[edit] IR PCB Connector

• Added series termination on TOUCH_SPI_CLK, TOUCH_SPI_SIMO
• Changed from 14 pin to 12 pin.

[edit] PQ58

• Swap the source and drain of PQ58

[edit] A2 Layout Fixes

[edit] IR PCB Connector

• Changed from 14 pin to 12 pin.
• Move CN5 over to avoid extra bends in FFC to IR PCB.

[edit] Planned Feature Changes

[edit] Add second serial port

Connect UART 1 up to a serial connector. As it is a +1.8V signal, add a level translator on the output signal and a voltage divider on the input. This can be depopulated for production.