XO PRS 2006

From OLPC

Revision as of 16:18, 30 December 2008 by Wad (Talk | contribs)
(diff) ← Older revision | Current revision (diff) | Newer revision → (diff)
Jump to: navigation, search

This is Jordan Crouse's investigation into a PRS (Processor Register Settings) run that Mitch Bradley conducted using early Open Firmware on the XO in October, 2006. Where applicable, Jordan includes comments from Tom Sylla (http://dev.laptop.org/attachment/ticket/109/prscheck.txt).

Contents

GX Graphics PCI Header Register

PCI Cache Line Size (R/W)

Expected 8 Got 0

IGNORE. The VSA should fill these out so that the headers are spec compliant. Its unlikely that any of the drivers use these fields, so its probably OK to ignore these.

GX CPU Core MSRs

Data Memory Configuration (MSR 0x1800)

Expected 200000000002 Got 200000000022

FIX PRS. This is correct. It makes an INVD command work exactly like WBINVD. Interestingly enough, Tom's PRS check was different (it expected 200000000022), so that should be looked into.

Default RCONF (MSR 0x1808)

Expected 25fff00210730000 Got 25fff0021077e000

FIX CODE. From Tom: This one doesn't matter too much at runtime (after BIOS boot) It may as well match our PRS, since that is how we run all the time. The flashrom utility that is used to flash will have to turn off write protect as necessary. There is an interesting tangent though, what settings is LinuxBIOS using when booting? It could be something faster than uncacheable. Even more tangential, is their memcpy for shadowing the fastest it can be on our hardware?

RCONF Bypass (MSR 0x180A)

Expected 11 Got 0

FIX PRS. This is correct. From Tom: LinuxBIOS is right here. It is wrong in the olpc.prs. The LinuxBIOS value matches both the sparrow and norwich PRSes. '0' is the highest performance setting.

C0000-DFFFF RCONF

Expected 2121212121210101 Got 212121212121212

POSSIBLE CODE FIX. From Tom: this one would take some looking into. these regions are usually set CD, WS because they are where PCI ROMs are usually located. Since the OLPC will have no PCI ROMs at these locations, These could be made cacheable, and added back to the memory map that linux uses.
I'm not sure if we can even use this space in kernel land. - JordanCrouse (Talk to me!) 13:59, 3 October 2006 (EDT)

E0000 - FFFFF RCONF

Expected 101010101010101 Got 2121212121212121

POSSIBLE CODE FIX. Same as above.
I'm not sure we can use this space even if the kernel gets it back - JordanCrouse (Talk to me!) 13:59, 3 October 2006 (EDT)

Region Configuration SMM

Expected 4043f00040400104 Got 4041f00040400104

FIX PRS. I think this is fine - this just indicates that our SMM area is smaller then it normally is with the full VSA.

GX GeodeLink Memory Controller MSRs

Refresh and SDRAM program (0x20000018)

Expected 1007401200002000 Got 1007401200002400

VERIFY & FIX PRS. This needs to be verified correct for the hardware, and the PRS updated for the right value.

GX Display Filter (DF) MSRs

GLD Master Configuration (MSR 0xc0002001)

Expected 40f00 Got 40f80

FIX PRS. This value is correct for a TFT attached board.

GX GeodeLink Control Processor (GLCP) MSRs

I/O Delay Controls

Expected 830d415f8ea0ad6f Got 830d415a8ea0ad6a

FIX PRS - PRS is on crack here - the recieved value is correct for DDR.

MCP System Reset and PLL Control

Expected 21906de0078 Got 22606de0070

FIX CODE? - Bit 4 post divides the dotpll output frequency by 3. Is this needed?
Jordan will ask his local experts.
FIX PRS - Bits 32 to 37 are pseudo random due to the design of the PLL divider- the provided value should be fine.

GLCP DOT Clock PLL Control

Expected 9da02000000 Got 3702000000

FIX PRS - The dot clock DLL gets set in the fbdev driver - this value should be fine.

GLCP GLD Action Data Control

Expected 1b Got 0

??? - Jordan needs to look up this undocumented register

GLCP GLD Action Data

Expected 1001 Got 0

??? - Jordan needs to look up this undocumented register

GX GeodeLink PCI (GLPCI) MSRs

Fixed Region Enables

Expected fff3ff Got f000ff

FIX PRS? We are not enabling memory access to the following regions through PCI - unsure if any of these are used by the software: C0,C4,D0,D4,D8,DC,E0,E4,E8,EC
I think that this is set by VSA - Jordan needs to verify.

Memory Region 1 Configuration

Expected 77bf00000100130 Got 77df00000100130

FIX PRS - This is probably OK - the memory for this region is put a few K higher then it is on normal geode boxes.

Memory Region 2 Configuration

 exp 4043f00040400120
 got 4041f00040400120
FIX PRS - This is probably OK - the memory for this region is put a few K higher then it is on normal geode boxes.

CS5536 ISA Bridge PCI Header Registers

PCI Command

Expected 9 Got 49

FIX PRS - The ParErr bit is enabled in the header, but it doesn't do anything.

PCI Cache Line Size(R/W)

Expected 8 Got 0

FIX LB - this is harmless, but should be properly set by LB PCI scan.


CS5536 Audio PCI Header Registers

PCI Command

Expected 5 Got 41

FIX PRS - The ParErr bit is enabled in the header, but it doesn't do anything.
FIX PRS - Bus mastering is enabled by the kernel driver.


PCI Cache Line Size(R/W)

Expected 8 Got 0

FIX LB - this is harmless, but should be properly set by LB PCI scan.

CS5536 USB OHCI PCI Header Registers

PCI Command

Expected 6 Got 2

FIX PRS - Bus mastering is enabled by the kernel driver.

PCI Cache Line Size(R/W)

Expected 8 Got 0

FIX LB - this is harmless, but should be properly set by LB PCI scan.

Reserved

Expected 0 Got ff000000

CHECK LB - this must be set by LB for reasons unknown.

Interrupt Line

Expected d Got a

'FIX PRD - this is fine - the chosen interrupt on this platform is 10.

CS5536 USB EHCI PCI Header Registers

PCI Command

Expected 6 Got 2

FIX PRS - Bus mastering is enabled by the kernel driver.

PCI Cache Line Size(R/W)

Expected 8 Got 0

FIX LB - this is harmless, but should be properly set by LB PCI scan.

Interrupt Line

Expected d Got a

FIX PRS - this is fine - the chosen interrupt on this platform is 10.

USB Legacy Support Extended Capability

Expected 0 Got 1

FIX PRS - this bit indicates legacy handoff of the legacy usb support - this doesn't make sense on the OLPC, so 1 is the right value here.

CS5536 SB

GeodeLink Global Control

Expected 44000040020a0013 Got 4400004000020013

FIX PRD - bit 15 - Controls the decoding of I/O range associated with the DMA high page registers - this is correctly set to be part of legacy I/O.
KERNEL PM - bit 23:21 - Busy Sustain - controls the sustain time for keeping the clocks running - this should be set by the kernel PM.

PCI Configuration Space Header Byte 8-C

Expected ff000002 Got ff000003

FIX PRD - The PRD needs to be updated for the CS5536 B1 revision.

CS5536 DIVIL

PIN_OPT (0x51400015)

Expected 71 Got 70

FIX PRD - bit 0 indicates if we are using FLASH or IDE - FLASH (0) is the right operation.

NANDF_DATA

Expected 7770777 Got 100010

FIX PRD or IGNORE - 7770777 is the default for this register - it is currently being programmed correctly for the CS5536 flash. Note that this can be ignored with the CAFE.

NANDF_CNTL

Expected 777 Got 10

FIX PRD or IGNORE - 777 is the default for this register - it is currently being programmed correctly for the CS5536 flash. Note that this can be ignored with the CAFE.

IRQM_YLOW

Expected aa0b0b00 Got bb050a00

FIX PRD - the USB IRQ (Yinput 2) is being pointed to interrupt 10 instead of interrupt 11 - this is fine.
FIX PRD - the Audio IRQ (Yinput 4) is being pointed to interrupt 5 instead of interrupt 11 - this is fine.
FIX PRD - the Nand Ready (Yinput 6) is being pointed to interrupt 11 instead of interrupt 10 - this is fine (unneeded with CAFE)
FIX PRD - the Nand Distraction (Yinput 7) is being pointed to interrupt 11 instead of interrupt 10 - this is fine (unneeded with CAFE)


IRQM_ZHIGH

Expected baba2 Got aa5b2

FIX PRD - these are the interrupt assignments for the PCI pins - they should be modified for the appropriate mappings (PCIA == 0x0B, the other 3 shold not be setup)

IRQM_LPC

Expected 10da Got 0

FIX PRD - these are the LPC interrupt maps - the only two sources we should be mapping is the keyboard and the mouse (bit 1 and bit 12) - the other devices we don't have. This should be 0x1002 (Per Mercury and Quantas).

DMA_MAP

Expected 7777 Got 0

FIX PRD - We probably don't need DMA for LPC

LPC_SIRQ

Expected ef2500c0 Got 0

FIX PRD - this should be set to 0xEFFD0080 for test-A, but it should go to 0xEFFD00C0 for test-B with the KB3700 (and when the EC firmware has changed).

CS5536 GPIO

GPIOL_OUTPUT_ENABLE (0x04)

Expected 3efdc102 Got 3effc100

FIX CODE GPIO1 output enable is disabled - GPIO1 is connected to the PC speaker function - it should be enabled for that purpose. Fix the code to enable this bit for output

GPIOL_OUT_AUX1_SELECT

Expected 3ffdc002 Got 3effc100

FIX CODE GPIO1 AUX1 select is disabled - AUX1 support is the PC beep functionality - that is the correct functionality for this pin. Code needs to be fixed.
FIX PRD GPIO8 AUX1 select is enabled - this enables UART1 functionality, which is correct for this platform.

GPIOL_PULLUP_ENABLE

Expected 30a1cf5e Got 3081cf7e

FIX PRD GPIO5 - Pullup is enabled. This can be reliably ignored, since the GPIO5 is connected to the DCON and is programmed as an input during DCON init.

GPIOL_PULLDOWN_ENABLE

Expected ffdf0020 Got ffff0000

FIX PRD - This is the inverse of the above - if pullup is enabled on GPIO5 then it cannot be pulled down. Either way, it doesn't matter.

GPIOL_INPUT_ENABLE

Expected d5af2a5 Got d7af285

FIX PRD GPIO5 is not configured for input - thats fine, since it is inited during DCON setup.

GPIOL_EVENTS_ENABLE

Expected cf7e3081 Got df7e2081

FIX PRD - GPIO12 is the DCONBLNK line - asserted by the DCON. It is fine if events are disabled on this bit since it will be correctly setup during DCON init

GPIOH_OUTPUT_ENABLE

Expected f6ff0900 Got ffff0000

EMAILED MARK - GPIO24 asserts the MAIN_ON line - This seems like it is essential for proper operation.
FIX PRD - GPIO27 is the SCI# coming from the EC - it is an input line, so output enable is not needed.

GPIOH_OUT_OPENDRAIN

Expected f7ff0800 Got ffff0000

FIX PRD - GPIO27 is the SCI# coming from the EC to the CS6636 - OUT_OPENDRAIN is not needed.

GPIOH_OUT_AUX1_SELECT

Expected f6ff0900 Got ffff0000

EMAILED MARK - AUX1 on GPIO24 asserts the MAIN_ON line - This seems like it is essential for proper operation.
FIX PRD - GPIO27 is the SCI# coming from the EC to the CS5536 - it is an input device, OUT_AUX1 is not needed.

GPIOH_ PULLUP_ENABLE

Expected 1000edff Got fdff

EMAILED MARK 10/17 - If we need to enable the power button functionality, then this should be enabled (see below).

GPIOH_IN_FILTER_ENABLE

Expected edff1000 Got fdff0000

EMAILED MARK 10/17 - If we need filtering on the GPIO28 line (POWER_BTN) for debouncing then it should be enabled, and the value in FILTER_AMOUNT (below) should be set.

GPIO_06_FILTER_AMOUNT

Expected 180 Got 0

EMAILED MARK 10/17 - Filter amount for the GPIO filtering function - if filtering is needed, this value should be used.

GPIO_MAPPER_W

Expected 80000 Got 0

EMAILED MARK 10/17 - This enables GPIO28 to fire an PME event when it is asserted. Unsure if this is needed with the EC

GPIO_FE_SELECT_6

Expected 1c Got 0

EMAILED MARK 10/17 - This selects GPIO28 (power button input) to be part of a filter group (see above).

CS5536 PMC

NOTE - These 5 reigsters control various delays related with suspending and resuming the system - they should be evaluated and set during the power management work in the kernel.

PM Sleep Clock Delay and Enable (0x10)

Expected e00 Got 0

KERNEL PM

PM Sleep End Delay (0x14)

Expected 4601 Got 0

PM Sleep Input Disable De-assert and Enable I/O

Expected 8c02 Got 0

KERNEL PM

PM Working De-assert Delay and Enable I/O

Expected a0 Got 0

KERNEL PM

PM Work_Aux De-assert Delay and Enable I/O

Expected a0 Got 0

KERNEL PM

PM Fail-safe Delay and Enable I/O

Expected 40020000 Got 0

UNKNOWN - E-MAILED MARK 10/17 - This register allows a fail-safe mechanism to fire and reset the system if the power button is pressed for N cycles. Since the power button on the OLPC goes through the EC, its unclear how the EC behaves in this situation, so we'll wait for Ray and Mark to respond.

CS5536 MFGPT

MFGPT 3 Setup

Expected 10da Got 30da

INVESTIGATE. Bit 13 indicates that the Comparator 1 output status is high. The clock isn't being actively used, so this is harmless in and of itself, but we need to investigate why VSA is setting up this clock. (Note - same goes for MFGPT 4 and MFGPT 5 setup).

MFGPT 5 CMP1

Expected 1b83 Got ffff

FIX PRS. The clock isn't being actively used, so the comparator value is harmless.

CS5536 SMB IO

SMBCTL2

Expected ff Got 41

FIX LB. SMBCTL[7:1] sets up the lower 7 bits of the SMB_CLOCK frequency. The kernel writes a 71 - Not sure where they got 41 from, but 71 has been verified to be a good value. Use that.

CS5536 EHC Native

USB_HCCPARAMS

Expected 5012 Got 12

FIX PRS. The 50 is used to point to an "extended capabilities" region in the config space.. Right now, that is only used to hand over control from the BIOS to the kernel. This isn't a problem for us, and we have no reason even to wander down this code in the first place, so keep the offset at 0, and fix the PRS.

IPGREG04

Expected 2 Got 0

FIX PRS. Undocumented bits - 0 is correct for OLPC. Update the PRS.
Personal tools
  • Log in
  • Login with OpenID
About OLPC
About the laptop
About the tablet
Projects
OLPC wiki
Toolbox