EC Register Settings: Difference between revisions
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<tr><td>0</td> <td>1</td> <td>OBF Interrupt enable. This bit enables KBC to generate interrupt to the core processor at the falling edge of OBF.</td></tr> |
<tr><td>0</td> <td>1</td> <td>OBF Interrupt enable. This bit enables KBC to generate interrupt to the core processor at the falling edge of OBF.</td></tr> |
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</table> |
</table> |
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* OFWDUMP 3 |
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**diff |
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===SCIE0=== |
===SCIE0=== |
Revision as of 03:42, 15 July 2007
NOTE: The contents of this page are not set in stone, and are subject to change! This page is a draft in active flux ... |
Current Embedded Controller register Settings
OFW Dump
using ec-dump.fth under OpenFirmware:
GPIOO fc00: 68 0 1e 0 GPIOE fc10: 7 d7 ff 1 b fd GPIOD fc20: e 91 0 0 9 60 GPIOIN fc30: fe b7 f7 e ff 71 2b GPIOPU fc40: 0 0 0 0 0 0 GPIOOD fc50: 0 80 0 0 GPIOIE fc60: 99 68 1e f f4 c0 34 GPIOM fc70: 1 KBC fc80: 60 43 0 ff ae f4 10 PWM fe00: 0 0 0 0 0 0 cf cf 0 80 80 0 ff ff GPT fe50: f 0 0 43 0 fa 27 10 0 20 SPI fea0: 0 0 0 0 0 64 4 0 0 0 0 0 0 4 0 0 WDT fe80: 0 0 0 70 5a 7 LPC fe90: 2 30 3 80 a0 fd 0 80 0 62 0 0 0 82 c0 1d PS2 fee0: 2f 0 21 76 1 af 2f EC ff00: a0 0 f 50 3 80 0 0 8c f0 83 20 12 94 52 95 0 0 1f 11 0 b 3e 83 9 0 0 0 0 20 37 0 GPWUEN ff30: 10 0 0 0 GPWUPF ff40: 89 8 16 c GPWUPS ff50: 0 8 0 0 GPWUEL ff60: 0 8 0 0
Register settings
GPIO General Purpose IO (include ADC, DAC)
GPIOO
Output Function Select
1 - Alt. output
0 - GPO
fc00: 68 0 1e 0
GPIOE
Output Enable
1 - Enable
0 - Disable
fc10: 7 d7 ff 1 b fd
GPIOD
Data Output
fc20: e 91 0 0 9 60
GPIOIN
Input Status
fc30: fe b7 f7 e ff 71 2b
GPIOPU
Pull Up Enable
fc40: 0 0 0 0 0 0
GPIOOD
Open Drain Enable
fc50: 0 80 0 0
GPIOIE
Input Enable
fc60: 99 68 1e f f4 c0 34
GPIOM
Misc
fc70: 1
KBC Keyboard Controller
fc80: 60 43 0 ff ae f4 10
KBCCB
KBC Command Byte
Bit | State | Description |
---|---|---|
7 | 0 | RSV |
6 | 1 | Scan Code Conversion |
5 | 1 | Auxiliary Device Disable |
4 | 0 | Keyboard Device Disable |
3 | 0 | Inhibit Override |
2 | 0 | System Flag |
1 | 0 | IRQ12 Enable |
0 | 0 | IRQ1 Enable |
KBCCFG
KBC Configuration
Bit | State | Description |
---|---|---|
7 | 0 | Keyboard Lock Enable |
6 | 1 | Fast Gate A20 Control |
5 | 0 | RSV |
4 | 0 | RSV |
3 | 0 | Keyboard Lock |
2 | 0 | RSV |
1 | 1 | IBF Interrupt Enable |
0 | 1 | OBF Interrupt Enable |
KBCIF
KBC Interrupt Flag Pending Flag
Bit | State | Description |
---|---|---|
7~3 | 0 | RSV |
2 | 0 | KBC Firmware mode in processing flag. Write 1 to exit firmware mode |
1 | 0 | IBF Interrupt pending flag |
0 | 0 | OBF Interrupt pending flag |
KBCHWEN
KBC Hardware Command Enable
Bit | State | Description |
---|---|---|
7 | 1 | FEh: KB Reset command processed by hardware |
6 | 1 | E0h: read test input command processed by hardware |
5 | 1 | D3h: write AUX output buffer |
4 | 1 | D2h: write KB output buffer |
3 | 1 | D1h: write P2 command command processed by hardware |
2 | 1 | D0h: read P2 command processed by hardware |
1 | 1 | C0h: read P0 command processed by hardware |
0 | 1 | 20h: read command byte processed by hardware |
KBCCMD
KBC Command Buffer The data written to IO port 64h will be stored in this register
KBCDAT
KBC Data IO Buffer' Writing to this register will cause OBF (Output Buffer Full) to set. Host reads this port through IO port 60h.
KBCSTS
KBC Host Status
Bit | State | Description |
---|---|---|
7 | 0 | Parity Error |
6 | 0 | Timeout |
5 | 0 | Auxiliary Data Flag |
4 | 0 | Uninhibited |
3 | 1 | Address (A2) |
2 | 0 | System Flag |
1 | 0 | IBF |
0 | 0 | OBF |
PWM Pulse Width Modulation
fe00: 0 0 0 0 0 0 cf cf 0 80 80 0 ff ff
PWMCFG
PWM Configuration
Bit | State | Description |
---|---|---|
7~6 | 0 | PWM1 Clock source selection |
5 | 0 | RSV |
4 | 0 | PWM1 Enable |
3~2 | 0 | PWM0 Clock source selection |
1 | 0 | RSV |
0 | 0 | PWM0 Enable |
PWMHIGH0
PWM0 High Period Length
0x00
PWMCYCL0
PWM0 Cycle Length
0x00
PWMHIGH1
PWM1 High Period Length
0x00
PWMCYCL1
PWM1 Cycle Length
0x00
PWMCFG2
PWM2 Configuration
Bit | State | Description |
---|---|---|
7 | 0 | PWM2 Enable |
6 | 0 | PWM prescaler clock select (0: peripheral clock, 1: 1Mhz clock) |
5~0 | 0 | 6-bit prescaler for PWM by selected clock |
PWMCFG3
PWM3 Configuration
Bit | State | Description |
---|---|---|
7 | 1 | PWM3 Enable |
6 | 1 | PWM prescaler clock select (0: peripheral clock, 1: 1Mhz clock) |
5~0 | 1111 | 6-bit prescaler for PWM by selected clock |
PWMCFG4
PWM4 Configuration
Bit | State | Description |
---|---|---|
7 | 1 | PWM4 Enable |
6 | 1 | PWM prescaler clock select (0: peripheral clock, 1: 1Mhz clock) |
5~0 | 1111 | 6-bit prescaler for PWM by selected clock |
PWMHIGH2
PWM2 High Period Length High byte
0x00
PWMHIGH3
PWM3 High Period Length High byte
0x80
PWMHIGH4
PWM4 High Period Length High byte
0x80
PWMCYC2
PWM2 Cycle Length High byte
0x00
PWMCYC3
PWM3 Cycle Length High byte
0xFF
PWMCYC4
PWM4 Cycle Length High byte
0xFF
GPT General Purpose 16-bit timer
fe50: f 0 0 43 0 fa 27 10 0 20
GPTCFG
GTP Configuration
Bit | State | Description |
---|---|---|
7~5 | 0 | RSV |
4 | 0 | GPT Test mode - GPT base clock will be system lcok |
3 | 1 | Enable GPT3 counting and interrupt |
2 | 1 | Enable GPT2 counting and interrupt |
1 | 1 | Enable GPT1 counting and interrupt |
0 | 1 | Enable GPT0 counting and interrupt |
GPTPF
GPT Pending Flag
Bit | State | Description |
---|---|---|
7 | 0 | Write 1 to start GPT3 |
6 | 0 | Write 1 to start GPT2 |
5 | 0 | Write 1 to start GPT1 |
4 | 0 | Write 1 to start GPT0 |
3 | 0 | GPT3 interrupt pending flag |
2 | 0 | GPT2 interrupt pending flag |
1 | 0 | GPT1 interrupt pending flag |
0 | 0 | GPT0 interrupt pending flag |
GPT0
GPT0 Count Value Once timer has reached this level, interrupt will occur and timer will restart from zero.
0x00
GPT1
GPT1 Count Value
0x43
GPT2H,L
GPT2 Count Value
0x00fa
GPT3H,L
GPT3 Count Value
0x2710
SPI
fea0: 0 0 0 0 0 64 4 0 0 0 0 0 0 4 0 0
Watchdog Timer
WDT fe80: 0 0 0 70 5a 7
WDTCFG
WDT Configuration
Bit | State | Description |
---|---|---|
7 | 0 | WDT Extended Bits Enable (0=20 bit timer) |
6~3 | 0000 | Force disable/set test mode/unset test mode |
2 | 0 | WDT Clock Selection for testing (0=normal) |
1 | 0 | Enable WDT interrupt |
0 | 0 | WDT timer reset |
WDTPF
WDT Pending Flag
Bit | State | Description |
---|---|---|
7~5 | 0 | RSV |
1 | 0 | If set, next WDT timeout event will cause WDT reset signal |
0 | 0 | WDT reset event pending |
WTDCNT
WDT 8-bit Count Value Once WDT reaches this value, interrupt will occur.
WTD Testing Counter Value
For testing WDT
fe83 19->12 fe84 11->04 fe85 03->00
LPC Low Pin Count
Low Pin Count / Firmware Hub
fe90: 2 30 3 80 a0 fd 0 80 0 62 0 0 0 82 c0 1d
PS2
PS2 Controller
fee0: 2f 0 21 76 1 af 2f
PS2CFG
PS2 Configuration
Bit | State | Description |
---|---|---|
7 | 0 | RSV |
6 | 0 | Enable PS2 port 2 |
5 | 1 | Enable PS2 port 1 |
4 | 0 | RSV |
3 | 1 | Enable interrupt of PS2 parity error |
2 | 1 | Enable interrupt of PS2 TX timeout |
1 | 1 | Enable interrupt of PS2 transmitted byte |
0 | 1 | Enable interrupt of PS2 received byte |
PS2PF
PS2 Pending Flag
Bit | State | Description |
---|---|---|
7 | 0 | RSV |
6 | 0 | Received byte port is PS2 port 2 |
5 | 0 | Received byte port is PS2 port 1 |
4 | 0 | RSV |
3 | 0 | Interrupt pending flag of PS2 parity error |
2 | 0 | Interrupt pending flag of PS2 TX timeout |
1 | 0 | Interrupt pending flag of PS2 PS2 transmitted byte |
0 | 0 | Interrupt pending flag of PS2 received byte |
PS2CTRL
PS2 Transmitter / Receiver Control
Bit | State | Description |
---|---|---|
7 | 0 | RSV |
6 | 0 | Transmit byte port is PS2 port 1 |
5 | 1 | Transmit byte port is PS2 port 1 |
4 | 0 | RSV |
3 | 0 | Force reset of PS2 transmitter state |
2 | 0 | Force reset of PS2 reciever state |
1 | 0 | Flag of PS2 RX timeout |
0 | 1 | Enable PS2 transmit data port - set to transmit byte over PS2DATA |
PS2DATA
PS2 Data
Read to get data of recieved byte from a PS2 device.
Write to transmit to a PS2 device. Will clear previous state.
PS2CFG2
PS2 Configuration 2
Bit | State | Description |
---|---|---|
7~2 | 0 | RSV |
1 | 0 | PS2 protocol waiting time enable |
0 | 1 | PS2CLK/PS2DAT input de-bounce enable (0: 1us, 1: 2us) |
PS2PINS
PS2 pin input status
Bit | State | Description |
---|---|---|
7 | 1 | RSV |
6 | 0 | PS2 port 2 clock |
5 | 1 | PS2 port 1 clock |
4 | 0 | RSV |
3 | 1 | RSV |
2 | 1 | PS2 port 2 data |
1 | 1 | PS2 port 1 data |
0 | 1 | RSV |
PS2PINO
PS2 pin output status
Bit | State | Description |
---|---|---|
7 | 0 | RSV |
6 | 0 | PS2 port 2 clock |
5 | 1 | PS2 port 1 clock |
4 | 0 | RSV |
3 | 1 | RSV |
2 | 1 | PS2 port 2 data |
1 | 1 | PS2 port 1 data |
0 | 1 | RSV |
EC Embedded Controller (hardware EC Space)
EC Registers
ff00: a0 0 f 50 3 80 0 0 8c f0 83 20 12 94 52 95 0 0 1f 11 0 b 3e 83 9 0 0 0 0 20 37 0
ECHV
EC Hardware Revision ID A0 (default)
- OFWDUMP same
ECFV
EC Firmware Revision ID 0 (default)
- OFWDUMP same
ECHA
EC High Address default (F)
Bit | State | Description |
---|---|---|
7~4 | 0 | foo |
3-0 | 1111 | High-byte address of 64Kbyte EC address base. |
- OFWDUMP same
SCICFG
SCI Configuration default (90)
Bit | State | Description |
---|---|---|
7 | 0 | Enable generation of SCI by standard EC commands (default enable) |
6 | 1 | Enable SCID port (Firmware generated SCI) |
5 | 0 | EC SCI pulse polarity (1 low active (default), 0 high active) |
4 | 1 | Enable EC SCI (set 1) from SCIIFx (default enabled) |
3~0 | 0 | SCI pluse width = SCIPW x 64us. if 0, pluse width is system clock |
- OFWDUMP 50
- diff
- EC SCI pulse polarity low active
- disabled EC SCI
- diff
ECCFG
EC Configuration default (0)
Bit | State | Description |
---|---|---|
7 | 0 | Enable EPB Fast Access |
6 | 0 | Test mode (Set to 0 for normal operation) |
5 | 0 | Enable hardware EC Read/Write command |
4 | 0 | Enable hardware EC Burst Enable/Disable command |
3 | 0 | Enable hardware EC Query command |
2 | 0 | Enable Extended IO port interrupt to 8051 |
1 | 1 | IBF Interrupt Enable. also be the Firmware Mode Enable. This bit enables KBC to generate interrupt to the 8051 at the rising edge of IBF, when the KBC command being received will be bypassed to firmware for processing. |
0 | 1 | OBF Interrupt enable. This bit enables KBC to generate interrupt to the core processor at the falling edge of OBF. |
- OFWDUMP 3
- diff
- diff
SCIE0
Enable extended 8051 Port0 interrupt to SCI default (0)
SCIE1
Enable extended 8051 Port1 interrupt to SCI default (0)
SCIE3
Enable extended 8051 Port3 interrupt to SCI default (0)
SCIF0
Flag for extended 8051 Port0 interrupt to SCI default (0)
SCIF1
Flag for extended 8051 Port1 interrupt to SCI default (0)
SCIF3
Flag for extended 8051 Port3 interrupt to SCI default (0)
SCID
EC SCI_ID Write port for 8051 firmware to generate SCI event default (0)
PMUCFG
PMU Control / Configuration default (2F)
Bit | State | Description |
---|---|---|
7 | 1 | Enable PLL enter low speed state in STOP mode |
6 | 0 | Flash (SPI) Interface Clock Control |
5 | 0 | Enable PLL to generate 32.768Mhz |
4 | 1 | Enable PLL enter low power state in STOP mode |
3~2 | 01 | 8051/Peripherals Normal Run Clock Selection
10: 22/8 MHz |
1 | 0 | Enable Peripheral Auto Slow Clock control to be 1Mhz |
0 | 0 | Enable 8051 IDLE mode slow clock control to be 1/2 Mhz |
CLKCFG
Clock Configuration default (00)
Bit | State | Description |
---|---|---|
7 | 0 | Enable PLL enter low speed state in STOP mode.
Set PLL frequency control value to be PLLLOW in STOP mode. The CLKCFG bit 4 should also be enabled for this option. |
6 | 0 | Flash (SPI) Interface Clock Control
|
5 | 0 | Enable PLL to generate a good 32.768MHz. (default reset PLL)
This bit should be set after PCICLK is stable. |
4 | 0 | Enable PLL enter low power state in STOP mode |
3-2 | 0 | 8051 / Peripherals Normal Run Clock Selection.
Clock rate is fixed in 2/1MHz when 8051 in IDLE if CLKCFG.0 is set. The flash interface (SPI or ISA) is fixed in 32.768 MHz or higher by CLKCFG.6 setting. |
1 | 0 | Enable Peripheral Auto Slow Clock Control to be 1 MHz.
The Peripheral's clock will be 1 MHz when no host accessing. |
0 | 0 | Enable 8051 IDLE Mode Slow Clock Control to be 2 / 1 MHz.
When 8051 enters IDLE state, the clock of 8051 and peripherals will changed automatically to 2 / 1 MHz. And the flash interface clock will be stop if this bit is set. |
EXTIO
EC Extended Write IO Data default (0)
PLLCFG
PLL Configuration default (70)
RSV
foo
CLKCFG2
Clock Configuration 2 default (1F)
PLLCFG2
PLL Configuration 2 default (11)
Bit | State | Description |
---|---|---|
7-6 | 0 | PLLINIT High Bits (PLLINITH)
High 2 bits of PLL frequency control initial value(PLLINIT). Combine with FF0Fh to be 10 bits frequency control value. |
5 | 0 | PLL Reference Selection
|
4 | 0 | PLL Source Clock Divider
The PLL build-in a 1024(10-bit) divider for source clock.For PLL reference clock is high speed, as PCICLK, the divider should be enabled. For PLL reference clock is low speed, as 32KHz from GPIO02 Alt. Input, the divider should be disabled. |
3~0 | 0 | PLL Low Speed State Setting
As Enable PLL enter low speed state in STOP mode, Use this value as PLL frequency control. |
PXCFG
8051 on-chip Control default (0)
Bit | State | Description |
---|---|---|
7~2 | 0 | RSV |
1 | 0 | Enable WDT timeout only reset 8051
(not including GPIO module) |
0 | 0 | Reset 8051 and 8051 internal peripherals(8051 serial port, timer, interrupt controller) . After reset, the 8051 will restart from reset vector if this bit is reset
to '0'. Write '1' to reset 8051. Write '0' to restart 8051. |
ADDAEN
ADC/DAC Enable default (0)
Bit | State | Description |
---|---|---|
7 | 0 | Select converting ADC channel 5 (Valid in A1 Version only) |
6 | 0 | Select converting ADC channel 4 (Valid in A1 Version only) |
5-0 | 0 | Enable ADC5~0 |
PLLFRH
PLL Frequency Register High Byte default (3E)
PLLFRL
PLL Frequency Register Low Byte default (83)
Bit | State | Description |
---|---|---|
7~4 | 0 | 32MHz clock count 32.768KHz value[3:0] |
3 | 0 | Enable show PLL lock value in CHIP ID reg |
2 | 0 | Enable PLL logic from test mode clock for testing. |
1~0 | 0 | Set PLL frequency count don't care bits
|
ADCTRL
ADC Control Register default (0)
Bit | State | Description |
---|---|---|
7-5 | 0 | RSV |
4-2 | 0 | Select converting ADC channel (ADC5~0)
NOTE: ONLY Channel 3~0 is valid in A0 and A1 version. All these three bit need to set ZERO if channel 4 or 5 selected using ADDAEN. |
1 | 0 | ADC test mode |
0 | 0 | Start (write 1 action ) ADC converter and Enable ADC converted interrupt |
ADCDAT
ADC Data output port After ADC converted, the value is held here. default (0)
ECIF
EC Interrupt Pending Flag default (0)
Bit | State | Description |
---|---|---|
7-3 | 0 | RSV |
2 | 0 | EC firmware mode in processing flag
Exit EC firmware mode and re-enable hardware mode by writing 1 |
1 | 0 | IBF interrupt pending flag, as ECSTS IBF is set by host write |
0 | 0 | OBF interrupt pending flag, as ECSTS OBF is clear by host read ECDAT
0 |
ECDAT
EC Data Port Window between host and EC default (0)
ECCMD
EC Command Port Stores the latest EC command from host. default (0)
ECSTS
EC Status port default (0)
Bit | State | Description |
---|---|---|
7 | 0 | Free r/w bit for host interface |
6 | 0 | Free r/w bit for host interface |
5 | 0 | SCI pending flag |
4 | 0 | Burst Enable Status |
3 | 0 |
A2 (Command or Data Flag)
|
2 | 0 | RSV |
1 | 0 | IBF, write IBF = 1 to clear IBF |
0 | 0 | OBF, write port ECDAT will set OBF to 1. Write OBF = 1 to clear OBF |
PLLVAL
Chip Part No. / PLL lock value (works if bit 3 of PLLFRL is enabled)
GPWU (hardware EC Space)
General Purpose Wake Up
GPWUEN ff30: 10 0 0 0 GPWUPF ff40: 89 8 16 c GPWUPS ff50: 0 8 0 0 GPWUEL ff60: 0 8 0 0
GPWU | 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
Event Enable | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Event Pending Flag | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
Polarity Selection | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Edge/Level Trigger Selection | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |