EC Register Settings

Current Embedded Controller register Settings

WORK IN PROGRESS

OFW Dump

GPIOO  fc00:   68  0 1e  0
GPIOE  fc10:    7 d7 ff  1  b fd
GPIOD  fc20:    e 91  0  0  9 60
GPIOIN fc30:   fe b7 f7  e ff 71 2b
GPIOPU fc40:    0  0  0  0  0  0
GPIOOD fc50:    0 80  0  0
GPIOIE fc60:   99 68 1e  f f4 c0 34
GPIOM  fc70:    1
KBC    fc80:   60 43  0 ff ae f4 10
PWM    fe00:    0  0  0  0  0  0 cf cf  0 80 80  0 ff ff
GPT    fe50:    f  0  0 43  0 fa 27 10  0 20
SPI    fea0:    0  0  0  0  0 64  4  0  0  0  0  0  0  4  0  0
WDT    fe80:    0  0  0 70 5a  7
LPC    fe90:    2 30  3 80 a0 fd  0 80  0 62  0  0  0 82 c0 1d
PS2    fee0:   2f  0 21 76  1 af 2f
EC     ff00:   a0  0  f 50  3 80  0  0 8c f0 83 20 12 94 52 95  0  0 1f 11  0  b 3e 83  9  0  0  0  0 20 37  0
GPWUEN ff30:   10  0  0  0
GPWUPF ff40:   89  8 16  c
GPWUPS ff50:    0  8  0  0
GPWUEL ff60:    0  8  0  0

Register settings

GPIO

GPIOO

Output Function Select

1 - Alt. output

0 - GPO

fc00:   68  0 1e  0

GPIOE

Output Enable

1 - Enable

0 - Disable

fc10:    7 d7 ff  1  b fd

GPIOD

Data Output

fc20:    e 91  0  0  9 60

GPIOIN

Input Status

fc30:   fe b7 f7  e ff 71 2b

GPIOPU

Pull Up Enable

fc40:    0  0  0  0  0  0

GPIOOD

Open Drain Enable

fc50:    0 80  0  0

GPIOIE

Input Enable

fc60:   99 68 1e  f f4 c0 34

GPIOM

Misc

fc70:    1

KBC

fc80:   60 43  0 ff ae f4 10

PWM

fe00:    0  0  0  0  0  0 cf cf  0 80 80  0 ff ff

GPT

fe50:    f  0  0 43  0 fa 27 10  0 20

SPI

fea0:    0  0  0  0  0 64  4  0  0  0  0  0  0  4  0  0

Watchdog Timer

WDT    fe80:    0  0  0 70 5a  7

WDTCFG

WDT Configuration

Bit	State	Description
7	0	WDT Extended Bits Enable (0=20 bit timer)
6~3	0000	Force disable/set test mode/unset test mode
2	0	WDT Clock Selection for testing (0=normal)
1	0	Enable WDT interrupt
0	0	WDT timer reset

WDTPF

WDT Pending Flag

Bit	State	Description
7~5	0	RSV
1	0	If set, next WDT timeout event will cause WDT reset signal
0	0	WDT reset event pending

WTDCNT

WDT 8-bit Count Value Once WDT reaches this value, interrupt will occur.

WTD Testing Counter Value

For testing WDT

fe83 19->12
fe84 11->04
fe85 03->00

LPC

Low Pin Count / Firmware Hub

fe90:    2 30  3 80 a0 fd  0 80  0 62  0  0  0 82 c0 1d

PS2

PS2 Controller

fee0:   2f  0 21 76  1 af 2f

EC

EC Registers

ff00:   a0  0  f 50  3 80  0  0 8c f0 83 20 12 94 52 95  0  0 1f 11  0  b 3e 83  9  0  0  0  0 20 37  0

GPW

General Purpose Wake Up

GPWUEN ff30:   10  0  0  0
GPWUPF ff40:   89  8 16  c
GPWUPS ff50:    0  8  0  0
GPWUEL ff60:    0  8  0  0