Memory Bit Mapping

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Occasionally, the need arises to map persistent errors on a particular data bit to a specific memory chip. This page provides that information for the XO Laptops.

It is strongly recommended that all memory chips be replaced if an error is encountered, as the process of replacing one will frequently damage other (strongly thermally coupled) memory chips.

XO-1

In XO-1, the AMD CS5336 Companion Chip supports a 64b bus. This is always populated with four 128M x 16b chip.

XO-1.5

On the XO-1.5, the Via VX855 Companion Chip supports either a 32b or 64b memory bus. There were two memory sizes produced: 512MB (32b bus) and 1GB (64b bus). Each memory chip handles 8b of data (128Mx8).

XO-1.5 512MB Memory Bit Mapping

Error	Byte	Data bits	Location
XX000000	3	31:24	U13
00XX0000	2	23:16	U12
0000XX00	1	15:8	U7
000000XX	0	7:0	U6

On XO-1.5 laptops with 1GB of main memory, the 64b memory bus means that the address of the failing 32b word is significant:

XO-1.5 1GB Memory Bit Mapping

Address	Error	Byte	Data bits	Location
even	XX000000	3	31:24	U13
	00XX0000	2	23:16	U12
	0000XX00	1	15:8	U7
	000000XX	0	7:0	U6
odd	XX000000	7	63:56	U15
	00XX0000	6	55:48	U9
	0000XX00	5	47:40	U8
	000000XX	4	39:32	U14

XO-1.75

On XO-1.75, the Marvell Armada 610 SoC has a 32b memory bus. Each memory chip handles 8b of data (either 128Mx8 or 256Mx8). The mapping between bits and memory is:

XO-1.75 Memory Bit Mapping

Error	Byte	Data bits	Location
XX000000	3	31:24	U6, R194, R195, R50
00XX0000	2	23:16	U12, R219, R220, R116
0000XX00	1	15:8	U7, R203, R206, R62
000000XX	0	7:0	U13, R214, R215, R120