Memory Bit Mapping: Difference between revisions

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==XO-1==
==XO-1==
In XO-1, the AMD CS5336 Companion Chip supports a 64b bus. This is always populated with four 128M x 16b chip.
In [[XO-1]], the [http://support.amd.com/us/Embedded_TechDocs/33238G_cs5536_db.pdf AMD CS5336 Companion Chip] supports a 64b bus. Each DDR1 memory chip handles two bytes of data (64M x 16b). The 64b address bus means that the address of the failing 32b word is significant:

{| border="1" align="center" cellpadding="6"
|+ '''[[XO-1]] 512MB Memory Bit Mapping'''
|- align="center"
|'''Address'''
|'''Error'''
|'''Byte'''
|'''Data bits'''
|'''Location'''
|- align="center"
|rowspan=4|even
|XXXX0000
|2 & 3
|31:16
|'''U30''', RN6, RN7, RN9, RN10, RP4, RP6
|- align="center"
|0000XXXX
|0 & 1
|15:0
|'''U34''', RN1, RN2, RN4, RN5, RP5, RP7
|- align="center"
|rowspan=4|odd
|XXXX0000
|6 & 7
|63:48
|'''U22''', RN16, RN17, RN19, RN20, RP8, RP9
|- align="center"
|0000XXXX
|4 & 5
|47:32
|'''U25''', RN11, RN12, RN14, RN15, RP10, RP11
|}


==XO-1.5==
==XO-1.5==
On the [[XO-1.5]], the Via VX855 Companion Chip supports either a 32b or 64b memory bus. There were two memory sizes produced: 512MB (32b bus) and 1GB (64b bus). Each memory chip handles 8b of data (128Mx8).
On the [[XO-1.5]], the [http://www.via.com.tw/en/products/chipsets/v-series/vx855 Via VX855 Companion Chip] supports either a 32b or 64b memory bus. There were two memory sizes produced: 512MB (32b bus) and 1GB (64b bus). Each DDR2 memory chip handles 8b of data (128Mx8).


{| border="1" align="center" cellpadding="6"
{| border="1" align="center" cellpadding="6"
Line 22: Line 54:
|3
|3
|31:24
|31:24
|'''U13''', RN6, RN8, RN12, R139
|U13
|- align="center"
|- align="center"
|00XX0000
|00XX0000
|2
|2
|23:16
|23:16
|'''U12''', RN11, RN15, RN16, R144
|U12
|- align="center"
|- align="center"
|0000XX00
|0000XX00
|1
|1
|15:8
|15:8
|'''U7''', RN23, RN29, RN31, R156
|U7
|- align="center"
|- align="center"
|000000XX
|000000XX
|0
|0
|7:0
|7:0
|'''U6''', RN21, RN27, RN30, R153
|U6
|}
|}


Line 57: Line 89:
|3
|3
|31:24
|31:24
|'''U13''', RN6, RN8, RN12, R139
|U13
|- align="center"
|- align="center"
|00XX0000
|00XX0000
|2
|2
|23:16
|23:16
|'''U12''', RN11, RN15, RN16, R144
|U12
|- align="center"
|- align="center"
|0000XX00
|0000XX00
|1
|1
|15:8
|15:8
|'''U7''', RN23, RN29, RN31, R156
|U7
|- align="center"
|- align="center"
|000000XX
|000000XX
|0
|0
|7:0
|7:0
|'''U6''', RN21, RN27, RN30, R153
|U6
|- align="center"
|- align="center"
|rowspan=4|odd
|rowspan=4|odd
Line 78: Line 110:
|7
|7
|63:56
|63:56
|'''U15''', RN4, RN5, RN10, R143
|U15
|- align="center"
|- align="center"
|00XX0000
|00XX0000
|6
|6
|55:48
|55:48
|'''U9''', RN20, RN26, RN32, R154
|U9
|- align="center"
|- align="center"
|0000XX00
|0000XX00
|5
|5
|47:40
|47:40
|'''U8''', RN18, RN22, RN33, R157
|U8
|- align="center"
|- align="center"
|000000XX
|000000XX
|4
|4
|39:32
|39:32
|'''U14''', RN3, RN7, RN14, R137
|U14
|}
|}


==XO-1.75==
==XO-1.75==
On [[XO-1.75]], the Marvell Armada 610 SoC has a 32b memory bus. Each memory chip handles 8b of data (either 128Mx8 or 256Mx8). The mapping between bits and memory is:
On [[XO-1.75]], the [http://www.marvell.com/application-processors/armada-600/armada-610.jsp Marvell Armada 610 SoC] has a 32b memory bus. Each DDR3 memory chip handles 8b of data (either 128Mx8 or 256Mx8). The mapping between bits and memory is:


{| border="1" align="center" cellpadding="6"
{| border="1" align="center" cellpadding="6"

Revision as of 17:18, 20 April 2012

  This page is monitored by the OLPC team.

Occasionally, the need arises to map persistent errors on a particular data bit to a specific memory chip. This page provides that information for the XO Laptops.

It is strongly recommended that all memory chips be replaced if an error is encountered, as the process of replacing one will frequently damage other (strongly thermally coupled) memory chips.

XO-1

In XO-1, the AMD CS5336 Companion Chip supports a 64b bus. Each DDR1 memory chip handles two bytes of data (64M x 16b). The 64b address bus means that the address of the failing 32b word is significant:

XO-1 512MB Memory Bit Mapping
Address Error Byte Data bits Location
even XXXX0000 2 & 3 31:16 U30, RN6, RN7, RN9, RN10, RP4, RP6
0000XXXX 0 & 1 15:0 U34, RN1, RN2, RN4, RN5, RP5, RP7
odd XXXX0000 6 & 7 63:48 U22, RN16, RN17, RN19, RN20, RP8, RP9
0000XXXX 4 & 5 47:32 U25, RN11, RN12, RN14, RN15, RP10, RP11

XO-1.5

On the XO-1.5, the Via VX855 Companion Chip supports either a 32b or 64b memory bus. There were two memory sizes produced: 512MB (32b bus) and 1GB (64b bus). Each DDR2 memory chip handles 8b of data (128Mx8).

XO-1.5 512MB Memory Bit Mapping
Error Byte Data bits Location
XX000000 3 31:24 U13, RN6, RN8, RN12, R139
00XX0000 2 23:16 U12, RN11, RN15, RN16, R144
0000XX00 1 15:8 U7, RN23, RN29, RN31, R156
000000XX 0 7:0 U6, RN21, RN27, RN30, R153


On XO-1.5 laptops with 1GB of main memory, the 64b memory bus means that the address of the failing 32b word is significant:

XO-1.5 1GB Memory Bit Mapping
Address Error Byte Data bits Location
even XX000000 3 31:24 U13, RN6, RN8, RN12, R139
00XX0000 2 23:16 U12, RN11, RN15, RN16, R144
0000XX00 1 15:8 U7, RN23, RN29, RN31, R156
000000XX 0 7:0 U6, RN21, RN27, RN30, R153
odd XX000000 7 63:56 U15, RN4, RN5, RN10, R143
00XX0000 6 55:48 U9, RN20, RN26, RN32, R154
0000XX00 5 47:40 U8, RN18, RN22, RN33, R157
000000XX 4 39:32 U14, RN3, RN7, RN14, R137

XO-1.75

On XO-1.75, the Marvell Armada 610 SoC has a 32b memory bus. Each DDR3 memory chip handles 8b of data (either 128Mx8 or 256Mx8). The mapping between bits and memory is:

XO-1.75 Memory Bit Mapping
Error Byte Data bits Location
XX000000 3 31:24 U6, R194, R195, R50
00XX0000 2 23:16 U12, R219, R220, R116
0000XX00 1 15:8 U7, R203, R206, R62
000000XX 0 7:0 U13, R214, R215, R120
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