Geode instruction set

see Hardware specification and AMD's Geode LX data book

Overview

Generally speaking, the Geode processor supports the i686 (Pentium Pro) instruction set plus MMX, the parts of SSE that do not involve SSE registers or prefetch, and 3DNow! Enhanced. It also supports a couple Geode-specific instructions and a few SSE2 instructions.

There are also numerous kernel-only instructions and MSRs for dealing with an extra debug mode, for directly loading and saving the normally-hidden segment state (base, limit, etc.) and so on.

Geode-specific 3DNow! instructions

PFRCPV

Opcode "0F 0F / 86" is "PFRCPV xr,xr/m64" or "PFRCPV Pq,Qq". It performs floating-point reciprocal approximation for a pair of 32-bit floats in an MMX register. It is like the PFRCP instruction, except that it operates on a pair of values.

PFRSQRTV

Opcode "0F 0F / 86" is "PFRSQRTV xr,xr/m64" or "PFRSQRTV Pq,Qq". It performs floating-point reciprocal square root approximation for a pair of 32-bit floats in an MMX register. It is like the PFRSQRT instruction, except that it operates on a pair of values.

useful "undocumented" instructions

INT1

Opcode "F1" is "INT1", a 1-byte version of the "INT 1" ("CD 01") instruction. This instruction is also known as ICEBP, and is in fact available (but mostly undocumented) on all x86 processors since the 80386.

SALC

Opcode "D6" is "SALC", documented as "SETALC" with an incorrect description. This instruction sets all bits of AL to the carry flag. As with INT1, this instruction is available on all processors.

supported SSE1

PAVGB

packed average of unsigned byte, a=(a+b+1)/2 for 8 bytes

PAVGW

packed average of unsigned word, a=(a+b+1)/2 for 4 words

MASKMOVQ

cache-bypassing MMX store with byte mask (uses edi as destination)

MOVNTQ

cache-bypassing MMX store

PEXTRW

extract word into integer register, copies any word from an MMX register into a regular register

PINSRW

insert word, copies any word from memory or an integer register into an MMX register

PMAXSW

signed max() on MMX words

PMAXUB

unsigned max() on MMX bytes

PMINSW

signed min() on MMX words

PMINUB

unsigned min() on MMX bytes

PMOVMSKB

move byte mask (MSB of MMX bytes) to integer register

PMULHUW

packed multiply high unsigned word (useful for division)

PREFETCHNTA

prefetch using NTA register

PREFETCH0

prefetch using T0 register

PREFETCH1

prefetch using T1 register

PREFETCH2

prefetch using T2 register

PSADBW

packed sum of absolute byte differences

PSHUFW

packed shuffle word

SFENCE

store fence (see mfence)

unsupported SSE1

ADDPS ADDSS ANDNPS ANDPS CMPPS CMPSS COMISS CVTPI2PS CVTPS2PI CVTSI2SS CVTSS2SI CVTTPS2PI CVTTSS2SI DIVPS DIVSS LDMXCSR MAXPS MAXSS MINPS MINSS MOVAPS MOVHLPS MOVHPS MOVLHPS MOVLPS MOVNTPS MOVSS MOVUPS MULPS MULSS ORPS RCPPS RCPSS RSQRTPS RSQRTSS SHUFPS SQRTPS SQRTSS STMXCSR SUBPS SUBSS UCOMISS UNPCKHPS UNPCKLPS XORPS

supported SSE2

clflush

unprivileged cache line write back and invalidate (use "+m" for inline asm)

lfence

load fence (see mfence)

mfence

any load or store before the mfence is globally ordered with respect to any load or store after the mfence. This is needed when non-temporal operations are in use.

pause

really just a "rep nop", to give other CPUs a chance