Geode instruction set: Difference between revisions
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(a bit of SSE2 even) |
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See [[Hardware specification]], [[Geode]], and [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234E_LX_databook.pdf AMD's Geode LX data book]. |
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==Overview== |
==Overview== |
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Generally speaking, the '''Geode''' processor supports the '''i686''' (Pentium Pro) instruction set |
Generally speaking, the '''Geode''' processor is like the original Athlon. It supports the '''i686''' (Pentium Pro) instruction set, '''MMX''', the '''parts of SSE''' that do not involve SSE registers, '''3DNow! Enhanced''', a couple Geode-specific instructions and a few SSE2 instructions. |
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There are also numerous kernel-only instructions and MSRs for dealing with an extra debug mode, for directly loading and saving the normally-hidden segment state (base, limit, etc.) and so on. |
There are also numerous kernel-only instructions and MSRs for dealing with an extra debug mode, for directly loading and saving the normally-hidden segment state (base, limit, etc.) and so on. |
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==Geode-specific 3DNow! instructions== |
==Geode-specific 3DNow! instructions== |
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;PFRCPV: Opcode "0F 0F / 86" is "PFRCPV xr,xr/m64" or "PFRCPV Pq,Qq". It performs floating-point reciprocal approximation for a pair of 32-bit floats in an MMX register. It is like the PFRCP instruction, except that it operates on a pair of values. |
;PFRCPV: Opcode "0F 0F / 86" is "PFRCPV xr,xr/m64" or "PFRCPV Pq,Qq". It performs floating-point reciprocal approximation for a pair of 32-bit floats in an MMX register. It is like the PFRCP instruction, except that it operates on a pair of values. |
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;PFRSQRTV: Opcode "0F 0F / |
;PFRSQRTV: Opcode "0F 0F / 87" is "PFRSQRTV xr,xr/m64" or "PFRSQRTV Pq,Qq". It performs floating-point reciprocal square root approximation for a pair of 32-bit floats in an MMX register. It is like the PFRSQRT instruction, except that it operates on a pair of values. |
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==useful "undocumented" instructions== |
==useful "undocumented" instructions== |
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;SFENCE: store fence (see mfence) |
;SFENCE: store fence (see mfence) |
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==unsupported SSE1== |
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ADDPS ADDSS ANDNPS ANDPS CMPPS CMPSS COMISS CVTPI2PS CVTPS2PI CVTSI2SS |
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CVTSS2SI CVTTPS2PI CVTTSS2SI DIVPS DIVSS LDMXCSR MAXPS MAXSS MINPS MINSS |
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MOVAPS MOVHLPS MOVHPS MOVLHPS MOVLPS MOVNTPS MOVSS MOVUPS MULPS MULSS ORPS |
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RCPPS RCPSS RSQRTPS RSQRTSS SHUFPS SQRTPS SQRTSS STMXCSR SUBPS SUBSS UCOMISS |
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UNPCKHPS UNPCKLPS XORPS |
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==supported SSE2== |
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;clflush: unprivileged cache line write back and invalidate (use "+m" for inline asm) |
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;lfence: load fence (see mfence) |
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;mfence: any load or store before the mfence is globally ordered with respect to any load or store after the mfence. This is needed when non-temporal operations are in use. |
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;pause: really just a "rep nop", to give other CPUs a chance |
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==Other== |
==Other== |
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Latest revision as of 20:07, 28 July 2008
See Hardware specification, Geode, and AMD's Geode LX data book.
Overview
Generally speaking, the Geode processor is like the original Athlon. It supports the i686 (Pentium Pro) instruction set, MMX, the parts of SSE that do not involve SSE registers, 3DNow! Enhanced, a couple Geode-specific instructions and a few SSE2 instructions.
There are also numerous kernel-only instructions and MSRs for dealing with an extra debug mode, for directly loading and saving the normally-hidden segment state (base, limit, etc.) and so on.
Geode-specific 3DNow! instructions
- PFRCPV
- Opcode "0F 0F / 86" is "PFRCPV xr,xr/m64" or "PFRCPV Pq,Qq". It performs floating-point reciprocal approximation for a pair of 32-bit floats in an MMX register. It is like the PFRCP instruction, except that it operates on a pair of values.
- PFRSQRTV
- Opcode "0F 0F / 87" is "PFRSQRTV xr,xr/m64" or "PFRSQRTV Pq,Qq". It performs floating-point reciprocal square root approximation for a pair of 32-bit floats in an MMX register. It is like the PFRSQRT instruction, except that it operates on a pair of values.
useful "undocumented" instructions
- INT1
- Opcode "F1" is "INT1", a 1-byte version of the "INT 1" ("CD 01") instruction. This instruction is also known as ICEBP, and is in fact available (but mostly undocumented) on all x86 processors since the 80386.
- SALC
- Opcode "D6" is "SALC", documented as "SETALC" with an incorrect description. This instruction sets all bits of AL to the carry flag. As with INT1, this instruction is available on all processors.
supported SSE1
- PAVGB
- packed average of unsigned byte, a=(a+b+1)/2 for 8 bytes
- PAVGW
- packed average of unsigned word, a=(a+b+1)/2 for 4 words
- MASKMOVQ
- cache-bypassing MMX store with byte mask (uses edi as destination)
- MOVNTQ
- cache-bypassing MMX store
- PEXTRW
- extract word into integer register, copies any word from an MMX register into a regular register
- PINSRW
- insert word, copies any word from memory or an integer register into an MMX register
- PMAXSW
- signed max() on MMX words
- PMAXUB
- unsigned max() on MMX bytes
- PMINSW
- signed min() on MMX words
- PMINUB
- unsigned min() on MMX bytes
- PMOVMSKB
- move byte mask (MSB of MMX bytes) to integer register
- PMULHUW
- packed multiply high unsigned word (useful for division)
- PREFETCHNTA
- prefetch using NTA register
- PREFETCH0
- prefetch using T0 register
- PREFETCH1
- prefetch using T1 register
- PREFETCH2
- prefetch using T2 register
- PSADBW
- packed sum of absolute byte differences
- PSHUFW
- packed shuffle word
- SFENCE
- store fence (see mfence)