XO4 A2 ECOs: Difference between revisions
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This corrects a problem with the BOM. If you have a board that prints the CForth banner on the serial port but then hangs, this is likely the issue. |
This corrects a problem with the BOM. If you have a board that prints the CForth banner on the serial port but then hangs, this is likely the issue. |
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* Swap PR66 |
* Swap PR66 and PR73. PR73 should be 10.7K and PR66 should be 64.9K |
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==New VCore== |
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This changes to lower Vcore values for debugging and normal operation (1.3 and 1.24V), |
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as well as a higher suspend voltage (1.0V) as suggested by Marvell for B0 silicon. |
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* PR62 (or PR57) should be 12.0K |
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* PR67 should be 18.0K |
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* PR66 should be 120K |
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* PR73 should be 30.0K |
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==Pulse JTAG Reset at start of day== |
==Pulse JTAG Reset at start of day== |
Revision as of 10:27, 7 August 2012
These are recommended engineering change orders (ECOs) to the A2 prototype of the XO-4 laptop. This is NOT a list of changes from A2 to B1, that is located elsewhere.
Fixing +3.3V_SOC
This fixes a problem where +3.3V_SOC doesn't quite turn on.
- Change PR79 to a 10K resistor
Fixing EC Programming by the SOC
This fixes the inability of the SOC to reprogram the EC.
- Add a 3K pullup resistor to +3.3V_NAND to EC_EDI_DO
Fix VCore
This corrects a problem with the BOM. If you have a board that prints the CForth banner on the serial port but then hangs, this is likely the issue.
- Swap PR66 and PR73. PR73 should be 10.7K and PR66 should be 64.9K
New VCore
This changes to lower Vcore values for debugging and normal operation (1.3 and 1.24V), as well as a higher suspend voltage (1.0V) as suggested by Marvell for B0 silicon.
- PR62 (or PR57) should be 12.0K
- PR67 should be 18.0K
- PR66 should be 120K
- PR73 should be 30.0K
Pulse JTAG Reset at start of day
Marvell added a requirement to assert JTAG reset only at the start of day.
- Add a small schottky between EN_+1.35V_DDR3 and PRI_TRST#. The cathode of the diode should be connected to EN_+1.35V_DDR3.
- Remove the 100K resistor from R335.
- Populate R334 with a 100K resistor.
Fix MMP3 B0 errata 1.15
- Replace R45 with a 10 ohm resistor
- Place three diodes in series between +1.8V_SOC_AVDD_FE (the side of R45 closest to the SOC) and GND, with the cathode connected to GND.
Changing to a +1.8V SPI Flash
Until we get the voltage translator working at SPI Flash speeds, we are disabling it and using a +1.8V 1 MByte SPI Flash ROM for U17.
- Depopulate R280 (0 ohm)
- Populate R281 with a 0 ohm resistor
- Populate R246 with a 120K resistor
- Replace U17 with a +1.8V SPI Flash
- Short Q27, pins 1 and 3
- Short Q28, pins 1 and 3
- Short Q29, pins 1 and 3
- Short D4, pins 1 and 2
Fixing SOC/EC Communications
This removes much of the voltage translation circuitry which was added to support an eventual change of masters in the EC/SOC SDI (SPI) bus. It fixes a reliability problem when talking to the EC.
- Remove the resistors from the following locations: R94 (3K), R98 (3K), R253 (3K), R258 (3K), R372 (1.2K), R373 (1.2K), and R375 (1.2K).
- Replace D18 with a 3K resistor.
- Remove Q38, and place a 3K resistor between pins 1 and 3
- Remove Q36, and place a 3K resistor between pins 1 and 3
- Add a 3K pullup resistor to +3.3VSUS_EC (or +3.3VSUS) to EC_SDI_MISO (Q37, pin 3).
- Add a 3.6K pulldown from SDI_MOSI (D18 anode) to GND
- Add a 3.6K pulldown from SDI_CLK (Q36.1) to GND
- Add a 3.6K pulldown from SDI_CS# (Q38.1) to GND
Alternate
An alternate fix for this problem was done to most boards:
- Add a 3K pullup resistor to +3.3VSUS_EC (or +3.3VSUS) to EC_SDI_MISO (Q37, pin 3).
- Add a 68 pF capacitor between Q36 pin 1 and GND