Geode instruction set: Difference between revisions
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==General== |
==General== |
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Generally speaking, the '''Geode''' processor supports the '''i686''' (Pentium Pro) instruction set plus '''MMX''' and '''3DNow! Enhanced''' |
Generally speaking, the '''Geode''' processor supports the '''i686''' (Pentium Pro) instruction set plus '''MMX''', the '''parts of SSE''' that do not involve SSE registers or prefetch, and '''3DNow! Enhanced'''. |
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==Geode-specific 3DNow! instructions== |
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==PFRCPV== |
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Opcode "0F 0F / 86" is "PFRCPV xr,xr/m64" or "PFRCPV Pq,Qq". It performs floating-point reciprocal approximation for a pair of 32-bit floats in an MMX register. It is like the PFRCP instruction, except that it operates on a pair of values. |
;PFRCPV: Opcode "0F 0F / 86" is "PFRCPV xr,xr/m64" or "PFRCPV Pq,Qq". It performs floating-point reciprocal approximation for a pair of 32-bit floats in an MMX register. It is like the PFRCP instruction, except that it operates on a pair of values. |
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==useful "undocumented" instructions== |
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==PFRSQRTV== |
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==INT1== |
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==SALC== |
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==Other== |
==Other== |
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Revision as of 20:08, 2 September 2007
General
Generally speaking, the Geode processor supports the i686 (Pentium Pro) instruction set plus MMX, the parts of SSE that do not involve SSE registers or prefetch, and 3DNow! Enhanced.
Geode-specific 3DNow! instructions
- PFRCPV
- Opcode "0F 0F / 86" is "PFRCPV xr,xr/m64" or "PFRCPV Pq,Qq". It performs floating-point reciprocal approximation for a pair of 32-bit floats in an MMX register. It is like the PFRCP instruction, except that it operates on a pair of values.
- PFRSQRTV
- Opcode "0F 0F / 86" is "PFRSQRTV xr,xr/m64" or "PFRSQRTV Pq,Qq". It performs floating-point reciprocal square root approximation for a pair of 32-bit floats in an MMX register. It is like the PFRSQRT instruction, except that it operates on a pair of values.
useful "undocumented" instructions
- INT1
- Opcode "F1" is "INT1", a 1-byte version of the "INT 1" ("CD 01") instruction. This instruction is also known as ICEBP, and is in fact available (but mostly undocumented) on all x86 processors since the 80386.
- SALC
- Opcode "D6" is "SALC", documented as "SETALC" with an incorrect description. This instruction sets all bits of AL to the carry flag. As with INT1, this instruction is available on all processors.
Other
There are numerous kernel-only instructions and MSRs for dealing with an extra debug mode, for directly loading and saving the normally-hidden segment state (base, limit, etc.) and so on.