EC Register Settings: Difference between revisions
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(New page: Current Embedded Controller register Settings '''WORK IN PROGRESS''' =OFW Dump= GPIOO fc00: 68 0 1e 0 GPIOE fc10: 7 d7 ff 1 b fd GPIOD fc20: e 91 0 0 9 60 GPIOIN fc...) |
(→Watchdog Timer: added info) |
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==Watchdog Timer== |
==Watchdog Timer== |
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WDT fe80: 0 0 0 70 5a 7 |
WDT fe80: 0 0 0 70 5a 7 |
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===WDTCFG=== |
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'''WDT Configuration''' |
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<table border="1" cellpadding="2" cellspacing="0"> |
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<tr><th>Bit</th> <th>State</th> <th>Description</th></tr> |
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<tr><td>7</td> <td>0</td> <td>WDT Extended Bits Enable (0=20 bit timer)</td></tr> |
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<tr><td>6~3</td> <td>0000</td><td>Force disable/set test mode/unset test mode</td></tr> |
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<tr><td>2</td> <td>0</td> <td>WDT Clock Selection for testing (0=normal)</td></tr> |
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<tr><td>1</td> <td>0</td> <td>Enable WDT interrupt</td></tr> |
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<tr><td>0</td> <td>0</td> <td>WDT timer reset</td></tr> |
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</table> |
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===WDTPF=== |
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'''WDT Pending Flag''' |
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<table border="1" cellpadding="2" cellspacing="0"> |
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<tr><th>Bit</th> <th>State</th> <th>Description</th></tr> |
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<tr><td>7~5</td> <td>0</td> <td>RSV</td></tr> |
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<tr><td>1</td> <td>0</td><td>If set, next WDT timeout event will cause WDT reset signal</td></tr> |
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<tr><td>0</td> <td>0</td> <td>WDT reset event pending</td></tr> |
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</table> |
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===WTDCNT=== |
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'''WDT 8-bit Count Value''' |
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Once WDT reaches this value, interrupt will occur. |
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===WTD Testing Counter Value=== |
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'''For testing WDT''' |
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fe83 19->12 |
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fe84 11->04 |
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fe85 03->00 |
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==LPC== |
==LPC== |
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Revision as of 05:46, 15 June 2007
Current Embedded Controller register Settings
WORK IN PROGRESS
OFW Dump
GPIOO fc00: 68 0 1e 0 GPIOE fc10: 7 d7 ff 1 b fd GPIOD fc20: e 91 0 0 9 60 GPIOIN fc30: fe b7 f7 e ff 71 2b GPIOPU fc40: 0 0 0 0 0 0 GPIOOD fc50: 0 80 0 0 GPIOIE fc60: 99 68 1e f f4 c0 34 GPIOM fc70: 1 KBC fc80: 60 43 0 ff ae f4 10 PWM fe00: 0 0 0 0 0 0 cf cf 0 80 80 0 ff ff GPT fe50: f 0 0 43 0 fa 27 10 0 20 SPI fea0: 0 0 0 0 0 64 4 0 0 0 0 0 0 4 0 0 WDT fe80: 0 0 0 70 5a 7 LPC fe90: 2 30 3 80 a0 fd 0 80 0 62 0 0 0 82 c0 1d PS2 fee0: 2f 0 21 76 1 af 2f EC ff00: a0 0 f 50 3 80 0 0 8c f0 83 20 12 94 52 95 0 0 1f 11 0 b 3e 83 9 0 0 0 0 20 37 0 GPWUEN ff30: 10 0 0 0 GPWUPF ff40: 89 8 16 c GPWUPS ff50: 0 8 0 0 GPWUEL ff60: 0 8 0 0
Register settings
GPIO
GPIOO
Output Function Select
1 - Alt. output
0 - GPO
fc00: 68 0 1e 0
GPIOE
Output Enable
1 - Enable
0 - Disable
fc10: 7 d7 ff 1 b fd
GPIOD
Data Output
fc20: e 91 0 0 9 60
GPIOIN
Input Status
fc30: fe b7 f7 e ff 71 2b
GPIOPU
Pull Up Enable
fc40: 0 0 0 0 0 0
GPIOOD
Open Drain Enable
fc50: 0 80 0 0
GPIOIE
Input Enable
fc60: 99 68 1e f f4 c0 34
GPIOM
Misc
fc70: 1
KBC
fc80: 60 43 0 ff ae f4 10
PWM
fe00: 0 0 0 0 0 0 cf cf 0 80 80 0 ff ff
GPT
fe50: f 0 0 43 0 fa 27 10 0 20
SPI
fea0: 0 0 0 0 0 64 4 0 0 0 0 0 0 4 0 0
Watchdog Timer
WDT fe80: 0 0 0 70 5a 7
WDTCFG
WDT Configuration
| Bit | State | Description |
|---|---|---|
| 7 | 0 | WDT Extended Bits Enable (0=20 bit timer) |
| 6~3 | 0000 | Force disable/set test mode/unset test mode |
| 2 | 0 | WDT Clock Selection for testing (0=normal) |
| 1 | 0 | Enable WDT interrupt |
| 0 | 0 | WDT timer reset |
WDTPF
WDT Pending Flag
| Bit | State | Description |
|---|---|---|
| 7~5 | 0 | RSV |
| 1 | 0 | If set, next WDT timeout event will cause WDT reset signal |
| 0 | 0 | WDT reset event pending |
WTDCNT
WDT 8-bit Count Value Once WDT reaches this value, interrupt will occur.
WTD Testing Counter Value
For testing WDT
fe83 19->12 fe84 11->04 fe85 03->00
LPC
Low Pin Count / Firmware Hub
fe90: 2 30 3 80 a0 fd 0 80 0 62 0 0 0 82 c0 1d
PS2
PS2 Controller
fee0: 2f 0 21 76 1 af 2f
EC
EC Registers
ff00: a0 0 f 50 3 80 0 0 8c f0 83 20 12 94 52 95 0 0 1f 11 0 b 3e 83 9 0 0 0 0 20 37 0
GPW
General Purpose Wake Up
GPWUEN ff30: 10 0 0 0 GPWUPF ff40: 89 8 16 c GPWUPS ff50: 0 8 0 0 GPWUEL ff60: 0 8 0 0