Hardware Power Domains

This is a working document summarizing some power-related aspects of the chips used in the OLPC system. Right now it is a barely-structured collection of notes gleaned from a read-through of the various chip specs, with an eye for stuff related to power management.

Please feel free to add information. Links to cited documents would be useful...

Geode GX

CPU Core

The main way to save power is to execute the HLT instruction when appropriate. This is the ACPI C1 state. GX has a feature called "suspend on hlt", which is always enabled, and causes the CPU core to "suspend" on every hlt, saving power.

• Suspend-on-Halt can be turned on and off by MSR 1210: This is on by default, and there is really no reason to turn it off.
• SMIs can be turned off with MSR 1301: Turning SMIs off is dangerous, PCI config space is emulated through SMM code.
• Real stamp and time stamp counters can count (or not) during suspend - MSR 1900: These settings are set to the correct values for compliant operation. Changing these settings will mess up all sorts of things in the system that use the tsc for timing.

Video

• Flat panel power management around page 377 of Geode manual (VP offset 0x410)
• Graphics processor can be turned off
• The video refresh compression feature will conserve power (and bandwidth) at the expense of increased memory usage
• Power down the DAC (both analog and digital sections) with Video MISC register (video base + 50h)

Other GX devices

MSR offset 2004 in each MBus device enables or disabled Active Hardware Clock Gating for that particular MBus device.

• GLIU0: 10002004 ("top" bus interface unit)
• GLIU1: 40002004 ("bottom" bus interface unit)
• MC: 20002004 (memory controller)
• GP: A0002004 (BLT engine)
• DC: 80002004 (display controller)
• VP: C0002004 (video processor)

Display controller has 4 different clocks.

There is a 200-clock delay from self-refresh exit to first read command. See MSR 2000001a. Note that this is a DDR spec, not a Geode spec.

Power mode sensitivity counters - MSR 20000020. Some experimentation could be done with these.

The Memory Controller's GLD_MSR_PM (MSR 20002004) is set to 3, enabling hardware and software clock gating. Software clock gating is determined by bits 33..32 of the MSR. Bit 32 controls gating on Power Mode 0, bit 33 controls gating on Power Mode 1.

5536 Companion Chip

• Clock domain list on page 63 of 33238f_cs5536_ds.pdf
• Power management overview on p 79
• More info on page 169

-> Note that the sections mentioned are describing the software and hardware architecture that is present on a normal GX/5536 system with an Insyde-type BIOS. Various pieces described there are not applicable to OLPC with LinuxBIOS.

• CPU supports clock stop (this really just means suspend-on-HLT)
• No support for optional ACPI Sleep state S2
• No support for ACPI CPU states C3 and CT

-> the throttling registers are actually present in GX, and they are fully documented. There were some errata with the hardware, but throttling may still work properly in many cases.

5536 hardware power states

• FO (Full On) - all clocks always running (state after reset)
• AHCG (Active Hardware Clock Gating) - hardware automatically stops/starts clocks transparently
• Suspend on Halt - ACPI G0/S0/C1
• Sleep - ACPI G1/S1/C2
• Auto-refresh - DRAM kept "warm" (support for ACPI G1/S3 state)

5536 Power domains

• Working Domain: Vcore and Vio
  • Includes everything not listed below
• Standby Domain: Vcore_vsb and Vio_vsb
  • GPIO[31:24]
  • GPIO input conditioning functions 6 and 7
  • GPIO power management events 6 and 7
  • MFGPT[7:6]
  • Power Management Controller (PMC) Standby Controller and its I/O (WORKING, WORK_AUX, RESET_OUT)
  • PMC Standby registers starting at PMS I/O Offset 30h.
• RTC Domain - Vbat
  • Real Time Clock (always on)

• WORKING output controls Working domain power to system memory
• WORK_AUX output controls Working domain power to everything else

System starts in Full On state. Switch to AHCG state via power management MSRs (section 6.18.1 page 526). Each functional block has such an MSR at xxxx.2004h.

5536 Power Management MSRs

• GLCP_GLD_MSR_PM 51700004 - enable AHCG
• There are 47 clocks that can be independently controlled on the 5536. Things like USB (13 different clocks), PCI, IDE, Audio, etc.

Other 5536 tests

The MSRs have several BISTs, for things like FPU internals, etc.

DCON Chip

Verbatim excerpts from the DCON spec:

Register 1 bits related to power

Bit 1: DCON Sleep Mode One key to the power efficiency of the DCON is its ability to enter a low power state in which the LCD is completely turned off, and the local SDRAM frame buffer is set to self-refresh mode – this mode is known as DCON Sleep Mode (or just Sleep mode). Under normal circumstances, the DCON will automatically enter Sleep mode as a result of prolonged system inactivity. Specifically, if the Auto Sleep Mode bit is set, and Display Timeout Value video output frames have occurred without a DisplayLoad cycle occurring, or an ECPWRRQST arriving, then the DCON will set this bit, and enter Sleep mode automatically.

Alternately, there are occasions where the CPU will need to initiate entry into DCON Sleep Mode. In particular, the CPU should manually enter Sleep mode when the power switch selects “System Off”, when the lid switch is closed, or when a critically low battery level is detected. To enter Sleep mode, this bit should be written with a ‘1’.

Since the frame buffer is held in the low power self-refresh state while the DCON is in Sleep mode, the DCON is unable to process incoming DisplayLoad cycles. However, the DCONLOAD pin is not ignored. If the CPU requests a DisplayLoad cycle while the DCON is in Sleep mode, this sets an internal state known as DCONLOAD_MISSED. This state is used to “remember” that the data in the frame buffer is no longer consistent with the latest display frame. When the DCON exits Sleep mode after missing DCONLOAD, it will automatically blank the screen, and will generate a DCONLOAD_MISSED interrupt by driving DCONIRQ active forone scan line. This allows the CPU to rewrite the latest frame, and then clear the Video Blanking pin to paint the newest information on the screen.

Exiting Sleep mode may be performed either manually or automatically. Under normal circumstances, this bit will be cleared automatically upon arrival of an ECPWRRQST. In other words, pressing a key restores the video display independently of the host CPU, thus “instantly” turning on the display when a keyboard key, cursor button, or the touchpad has been activated (this masks the latency that would otherwise be required for the CPU to enable the display). Alternately, if desired, the CPU may exit Sleep mode and reinitiate display refresh by clearing this bit to 0.

Bit 2: Auto Sleep Mode When this bit is set to 1, the DCON will automatically stop the display process after Display Timeout Value video frames have been output without system activity. Any time DCONLOAD is high, or when an incoming ECPWRRQST occurs, the internal display timeout register is automatically reset to the value in the Display Timeout Value register. If a Display Timeout occurs, the DCON will automatically enter Sleep mode by setting the DCON Sleep Mode bit to 1. When the Auto Sleep Mode bit is 0, the DCON will continue display refresh indefinitely, whether DisplayLoad cycles or ECPWRRQST occurs; in that case, Sleep mode may only be entered by writing to the DCON Sleep Mode bit.

Bit 3: Backlight Enable Backlight enable is used to determine whether the LCD’s backlight should be turned on while the display is enabled – set this to 1 to turn on the backlight whenever the DCON is not in DCON Sleep Mode. Note that it is not necessary for a screen saver to turn Backlight Enable on and off, since setting this bit allows the backlight to be enabled and disabled automatically (if this bit is left cleared, the backlight will remain disabled whether or not the DCON is on DCON Sleep Mode). When the Backlight is enabled, the BACKLIGHT pin will actively be driven high, and the DBC pin will be driven with a PWM waveform with a duty cycle that matches the value contained in the Backlight Brightness register.

Bit 4: Video Blanking Video blanking is used to display “black” on the screen, without affecting the contents of the DCON’s frame buffer, or the power state of the LCD. This feature is primarily used to determine whether the DCON should exit Sleep mode with the panel displaying data, or with the panel data masked off until the next DisplayLoad cycle. This is notably used by DCON itself. Since the DCON cannot record incoming DisplayLoad cycles while in Sleep mode, it will automatically set the VIDEO_BLANKING bit if DCONLOAD goes high while sleeping, thus ensuring that old data is not displayed upon wakeup. If this bit is written with a ‘1’, the panel will display “black”. If written with ‘0’, the current contents of the SDRAM frame buffer will be displayed on the screen.

Bits 9-11: DotClock Divider In order to support minimum power drain, the DCON supports the ability to reduce the frequency of the panel interface DotClock. The value in this field specifies the crystal oscillator divisor minus one, to yield the system DotClock frequency – all video timings are derived from DotClock. If this field contains 0, DotClock will be equal to the crystal’s clock frequency, whereas a value of 7 will yield a DotClock of 1/8th the crystal frequency. Using 4X the 14.31818 MHz crystal, and with nominal programmed video timing parameters that yield a 50 Hz panel refresh rate, varying the DotClock divider alone will result in actual panel refresh rates of 50.00 Hz, 25.00 Hz, 16.67 Hz, 12.50 Hz, 10.00 Hz, 8.33 Hz, 7.14 Hz, or 6.25 Hz.

Register 8: Display Timeout Value In order to save power, the DCON has the capability of automatically powering down the display outputs and entering DCON Sleep Mode. This register contains the number of output video frames before this automatic powerdown will occur – see the DCON Display Mode Register for more information on using this feature.

CaFe Chip (Camera and Flash Enabler)

Global register at offset 0x3004 can turn off individual module clocks to SD, NAND, and CC. Also, that register has a "ClkRun Enable Set/Clear" bit pair

SD Controller Section

In principle (i.e. if the simplified SD spec is fully implemented), it will be possible to gate the power to the SD card.

Camera Controller Section

The clock control register at offset 0x88 lets you turn off PIXCLK

Control 1 Register - offset 0x40 - has PWRDNEN to power down the controller.

The power to the external sensor is supposed to be controlled by a GPIO

NAND Controller Section

Assuming that the controller deasserts CE* after an access, the NAND FLASH chips will automatically enter a low-power standby state (10 uA typical).

Wireless Controller Chip

A station (client) (STA) can be in one of the three power management (PM) modes:

• Active mode (stays in Awake state)
• Power Save (PS) mode (stays in either Awake or Doze state)
• Deep sleep mode

When firmware enters PS mode, a number of hardware blocks are turned off (hardware MAC, baseband processor, and RF chip). A wakeup timer starts that wakes up the WLAN device at the next expected beacon transmit time from the AP. When in PS mode, the hardware bus interface to the host is turned off, as well.

Deep sleep mode:

The host may put the WLAN subsystem in Deep Sleep mode, during which the WLAN subsystem does not wakeup at all. The host sends a signal through the GPIO to wakeup the WLAN subsystem. The wakeup mechanism is interface-dependent.

• Wakeup semantics.

The firmware can be configured to wakeup the host under certain events. The various conditions are:

- Reception of any broadcast or multicast data (0x1)

- Reception of any unicast data (0x2)

- Generation of any MAC event (0x4)

The host always wakes up if any of the events corresponding to the link loss happens.

KB3700 Keyboard Controller Chip

• Sleep State - 8051 program counter stopped
• Deep Sleep State - all internal clocks stopped (~10 uA for 144-pin version)
• But resetting the keyboard controller hard-resets the system!
• Power consumption targets for 64-pin version: RUN: 12 mA, IDLE: 3 mA, STOP: 500 uA

Clock domains

• Flash - (16 MHz to 64 MHz)
• 8051/XBI - uses high clock (setting CLKCFG) 22~4 MHz (whatever that means)
• WDT - 32 kHz
• Other peripherals use low clock (CLKCFG), 8~2 MHz

CLKCFG register can dial down the clocks.

AD1888 Audio Codec Chip

• Unused channels can be disabled (it has more channels than the 2 we use)
• TBD need to read more about this chip

Power management test plan (work in progress)

This section should be moved to the power management software page.

Two issues:

1. Design verification for Quanta
2. Software to implement dynamic power management

Hardware Setup

• Measure input current with ammeter, or
• If possible, measure specific power domains with voltmeters across sense resistors.

TBD - determine whether such sense resistor test points are available.

C1 test

• Turn off unnecessary devices and disable most interrupts
• Wait for current to stabilize and record reading
• Setup RTC alarm to fire after N seconds
• Execute HLT instruction
• Record new current reading
• Verify that system wakes up after RTC alarm fires

TBD: do we need to test wakeup from other interrupt sources?

ACPI power states (reference)

This section is a brief summary of ACPI power states, for reference

Global states

• G0 - running
• G1 - suspended but system state is recoverable "quickly"
• G2 - off, requires reboot to start, but power supply is attached
• G3 - mechanical off, no wall power or main battery power (RTC battery possibly present)

System states

• G0/S0 - not sleeping
• G1/S1 - many clocks off, but state maintained inside devices
• G1/S3 - suspend to RAM - devices powered off, so their state must be saved in RAM (RAM must be powered)
• G1/S4 - suspend to disk (RAM not powered)
• G2/S5 - full reboot required. 32 kHz clock running.
• G3 - everything off, except optionally the RTC (mechanical off)

CPU states

• G0/S0/C0 - CPU actively executing instructions
• G0/S0/C1 - CPU halted (HLT), waiting for interrupt. Cache snoops working, so bus mastering is possible.
• G1/S1/C2 - Lowest CPU power state that maintains CPU internal context. No need for snooping because (per S1 rules) devices are inactive.
• G0/S0/CT - clock throttling (not supported by Geode)

Device states

PCI

(As per the Default Device Class Power Management Spec)

• D0 - Device is on and running
• D1 - This state is not defined and not used (Jordan says - I have never seen a PCI device that does D1)
• D2 - This state is not defined and not used (Jordan says - Dito)
• D3 - Device is off and not running. Device context is assumed lost.

USB

• D0

...

• D3

Other devices

• Most other on-board devices (i8402, graphics, southbridge gadets) are either on or off (so either D0 or D3 in ACPI speak).