EC Register Settings

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Revision as of 03:16, 15 June 2007 by Shenki (talk | contribs) (→‎GPW: added data)
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Current Embedded Controller register Settings

WORK IN PROGRESS

OFW Dump

GPIOO  fc00:   68  0 1e  0
GPIOE  fc10:    7 d7 ff  1  b fd
GPIOD  fc20:    e 91  0  0  9 60
GPIOIN fc30:   fe b7 f7  e ff 71 2b
GPIOPU fc40:    0  0  0  0  0  0
GPIOOD fc50:    0 80  0  0
GPIOIE fc60:   99 68 1e  f f4 c0 34
GPIOM  fc70:    1
KBC    fc80:   60 43  0 ff ae f4 10
PWM    fe00:    0  0  0  0  0  0 cf cf  0 80 80  0 ff ff
GPT    fe50:    f  0  0 43  0 fa 27 10  0 20
SPI    fea0:    0  0  0  0  0 64  4  0  0  0  0  0  0  4  0  0
WDT    fe80:    0  0  0 70 5a  7
LPC    fe90:    2 30  3 80 a0 fd  0 80  0 62  0  0  0 82 c0 1d
PS2    fee0:   2f  0 21 76  1 af 2f
EC     ff00:   a0  0  f 50  3 80  0  0 8c f0 83 20 12 94 52 95  0  0 1f 11  0  b 3e 83  9  0  0  0  0 20 37  0
GPWUEN ff30:   10  0  0  0
GPWUPF ff40:   89  8 16  c
GPWUPS ff50:    0  8  0  0
GPWUEL ff60:    0  8  0  0

Register settings

GPIO

GPIOO

Output Function Select

1 - Alt. output

0 - GPO 

fc00:   68  0 1e  0

GPIOE

Output Enable

1 - Enable

0 - Disable 

fc10:    7 d7 ff  1  b fd

GPIOD

Data Output 

fc20:    e 91  0  0  9 60

GPIOIN

Input Status 

fc30:   fe b7 f7  e ff 71 2b

GPIOPU

Pull Up Enable 

fc40:    0  0  0  0  0  0

GPIOOD

Open Drain Enable 

fc50:    0 80  0  0

GPIOIE

Input Enable 

fc60:   99 68 1e  f f4 c0 34

GPIOM

Misc 

fc70:    1


KBC

fc80:   60 43  0 ff ae f4 10

PWM

fe00:    0  0  0  0  0  0 cf cf  0 80 80  0 ff ff

GPT

fe50:    f  0  0 43  0 fa 27 10  0 20

SPI

fea0:    0  0  0  0  0 64  4  0  0  0  0  0  0  4  0  0

Watchdog Timer

WDT    fe80:    0  0  0 70 5a  7

WDTCFG

WDT Configuration

Bit State Description
7 0 WDT Extended Bits Enable (0=20 bit timer)
6~3 0000Force disable/set test mode/unset test mode
2 0 WDT Clock Selection for testing (0=normal)
1 0 Enable WDT interrupt
0 0 WDT timer reset

WDTPF

WDT Pending Flag

Bit State Description
7~5 0 RSV
1 0If set, next WDT timeout event will cause WDT reset signal
0 0 WDT reset event pending

WTDCNT

WDT 8-bit Count Value Once WDT reaches this value, interrupt will occur.

WTD Testing Counter Value

For testing WDT 

fe83 19->12
fe84 11->04
fe85 03->00

LPC

Low Pin Count / Firmware Hub 

fe90:    2 30  3 80 a0 fd  0 80  0 62  0  0  0 82 c0 1d

PS2

PS2 Controller 

fee0:   2f  0 21 76  1 af 2f

PS2CFG

PS2 Configuration

Bit StateDescription
7 0 RSV
6 0 Enable PS2 port 2
5 1 Enable PS2 port 1
4 0 RSV
3 1 Enable interrupt of PS2 parity error
2 1 Enable interrupt of PS2 TX timeout
1 1 Enable interrupt of PS2 transmitted byte
0 1 Enable interrupt of PS2 received byte

PS2PF

PS2 Pending Flag

Bit StateDescription
7 0 RSV
6 0 Received byte port is PS2 port 2
5 0 Received byte port is PS2 port 1
4 0 RSV
3 0 Interrupt pending flag of PS2 parity error
2 0 Interrupt pending flag of PS2 TX timeout
1 0 Interrupt pending flag of PS2 PS2 transmitted byte
0 0 Interrupt pending flag of PS2 received byte

PS2CTRL

PS2 Transmitter / Receiver Control

Bit StateDescription
7 0 RSV
6 0 Transmit byte port is PS2 port 1
5 1 Transmit byte port is PS2 port 1
4 0 RSV
3 0 Force reset of PS2 transmitter state
2 0 Force reset of PS2 reciever state
1 0 Flag of PS2 RX timeout
0 1 Enable PS2 transmit data port - set to transmit byte over PS2DATA

PS2DATA

PS2 Data

Read to get data of recieved byte from a PS2 device.

Write to transmit to a PS2 device. Will clear previous state.

PS2CFG2

PS2 Configuration 2

Bit StateDescription
7~2 0 RSV
1 0 PS2 protocol waiting time enable
0 1 PS2CLK/PS2DAT input de-bounce enable (0: 1us, 1: 2us)

PS2PINS

PS2 pin input status

Bit StateDescription
7 1 RSV
6 0 PS2 port 2 clock
5 1 PS2 port 1 clock
4 0 RSV
3 1 RSV
2 1 PS2 port 2 data
1 1 PS2 port 1 data
0 1 RSV

PS2PINO

PS2 pin output status

Bit StateDescription
7 0 RSV
6 0 PS2 port 2 clock
5 1 PS2 port 1 clock
4 0 RSV
3 1 RSV
2 1 PS2 port 2 data
1 1 PS2 port 1 data
0 1 RSV

EC

EC Registers 

ff00:   a0  0  f 50  3 80  0  0 8c f0 83 20 12 94 52 95  0  0 1f 11  0  b 3e 83  9  0  0  0  0 20 37  0

ECHV

EC Hardware Revision ID A0 (default)

ECFV

EC Firmware Revision ID 0 (default)

ECHA

EC High Address

Bit StateDescription
7~4 0 foo
3-0 1111 High-byte address of 64Kbyte EC address base.

SCICFG

SCI Configuration

Bit StateDescription
7 0 foo
6 0 foo
5 0 foo
4 0 foo
3 0 foo
2 0 foo
1 0 foo
0 0 foo

ECCFG

EC Configuration

Bit StateDescription
7 0 foo
6 0 foo
5 0 foo
4 0 foo
3 0 foo
2 0 foo
1 0 foo
0 0 foo

SCIE

SCIF

SCID

PMUCFG

PMU Control / Configuration

Bit StateDescription
7 0 foo
6 0 foo
5 0 foo
4 0 foo
3 0 foo
2 0 foo
1 0 foo
0 0 foo

CLKCFG

Clock Configuration

Bit StateDescription
7 0 foo
6 0 foo
5 0 foo
4 0 foo
3-2 0 foo
1 0 foo
0 0 foo

EXTIO

EC Extended Write IO Data


PLLCFG

PLL Configuration

CLKCFG2

Clock Configuration 2

PLLCFG2

PLL Configuration 2

Bit StateDescription
7-6 0 foo
5 0 foo
4 0 foo
3~0 0 foo

PXCFG

8051 on-chip Control

Bit StateDescription
7~1 0 RSV
1 0 foo
0 0 foo

ADDAEN

ADC/DAC Enable

Bit StateDescription
7 0 foo
6 0 foo
5=0 0 foo

PLLFRH

PLL Frequency Register High Byte

PLLFRL

PLL Frequency Register Low Byte

Bit StateDescription
7~4 0 foo
3 0 foo
2 0 foo
1~0 0 foo

ADCTRL

ADC Control Register

Bit StateDescription
7 0 RSV
4 0 foo
3 0 foo
2 0 foo
1 0 foo
0 0 foo

ADCDAT

ADC Data output port After ADC converted, the value is held here.

ECIF

EC Interrupt Pending Flag

Bit StateDescription
7 0 RSV
2 0 foo
1 0 foo
0 0 foo

ECDAT

EC Data Port Window between host and EC

ECCMD

EC Command Port Stores the latest EC command from host.

ECSTS

EC Status port

Bit StateDescription
7 0 foo
6 0 foo
5 0 foo
4 0 foo
3 0 foo
2 0 foo
1 0 foo
0 0 foo

GPWU

General Purpose Wake Up 

GPWUEN ff30:   10  0  0  0
GPWUPF ff40:   89  8 16  c
GPWUPS ff50:    0  8  0  0
GPWUEL ff60:    0  8  0  0
GPWU 0001020304050607 0809101112131415 1617181920212223 2425262728293031
Event Enable 00010000 00000000 00000000 00000000
Event Pending Flag 10001001 00001000 00010110 00001100
Polarity Selection 00001000 00000000 00000000 00000000
Edge/Level Trigger Selection 00001000 00000000 00000000 00000000
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