Memory Bit Mapping
Occasionally, the need arises to map persistent errors on a particular data bit to a specific memory chip. This page provides that information for the XO Laptops.
The factory repair procedure is to replace all memory chips if an error is encountered in any one of them, as the process of replacing one will frequently damage other (strongly thermally coupled) memory chips.
XO-1
In XO-1, the AMD CS5336 Companion Chip supports a 64b bus. Each DDR1 memory chip handles two bytes of data (64M x 16b). The 64b address bus means that the address of the failing 32b word is significant:
| Address | Error | Byte | Data bits | Location |
| odd | XXXX0000 | 6 & 7 | 63:48 | U22, RN16, RN17, RN19, RN20, RP8, RP9 |
| 0000XXXX | 4 & 5 | 47:32 | U25, RN11, RN12, RN14, RN15, RP10, RP11 | |
| even | XXXX0000 | 2 & 3 | 31:16 | U30, RN6, RN7, RN9, RN10, RP4, RP6 |
| 0000XXXX | 0 & 1 | 15:0 | U34, RN1, RN2, RN4, RN5, RP5, RP7 |
XO-1.5
On the XO-1.5, the Via VX855 Companion Chip supports either a 32b or 64b memory bus. There were two memory sizes produced: 512MB (32b bus) and 1GB (64b bus). Each DDR2 memory chip handles 8b of data (128Mx8).
| Error | Byte | Data bits | Location |
| XX000000 | 3 | 31:24 | U13, RN6, RN8, RN12, R139 |
| 00XX0000 | 2 | 23:16 | U12, RN11, RN15, RN16, R144 |
| 0000XX00 | 1 | 15:8 | U7, RN23, RN29, RN31, R156 |
| 000000XX | 0 | 7:0 | U6, RN21, RN27, RN30, R153 |
On XO-1.5 laptops with 1GB of main memory, the 64b memory bus means
that the address of the failing 32b word is significant:
| Address | Error | Byte | Data bits | Location |
| odd | XX000000 | 7 | 63:56 | U15, RN4, RN5, RN10, R143 |
| 00XX0000 | 6 | 55:48 | U9, RN20, RN26, RN32, R154 | |
| 0000XX00 | 5 | 47:40 | U8, RN18, RN22, RN33, R157 | |
| 000000XX | 4 | 39:32 | U14, RN3, RN7, RN14, R137 | |
| even | XX000000 | 3 | 31:24 | U13, RN6, RN8, RN12, R139 |
| 00XX0000 | 2 | 23:16 | U12, RN11, RN15, RN16, R144 | |
| 0000XX00 | 1 | 15:8 | U7, RN23, RN29, RN31, R156 | |
| 000000XX | 0 | 7:0 | U6, RN21, RN27, RN30, R153 |
XO-1.75
On XO-1.75, the Marvell Armada 610 SoC has a 32b memory bus. Each DDR3 memory chip handles 8b of data (either 128Mx8 or 256Mx8). The mapping between bits and memory is:
| Error | Byte | Data bits | Location |
| XX000000 | 3 | 31:24 | U6, R194, R195, R50 |
| 00XX0000 | 2 | 23:16 | U12, R219, R220, R116 |
| 0000XX00 | 1 | 15:8 | U7, R203, R206, R62 |
| 000000XX | 0 | 7:0 | U13, R214, R215, R120 |
XO-4
On the PXA2128 (MMP3), there are two memory controllers, each addressing a 32b bank of memory. The interleaving between the two memory controllers is programmable.
If a laptop has 2 GByte of memory, the interleave is set to 1 GB by default, and the following applies:
| Address | Error | Byte | Data bits | Location |
| < 1GB | XX00XX00 | 3,1 | 31:24, 15:8 | U21, RP5, RP6, RP7, RP8, RP14, RP15, R380 |
| 00XX00XX | 2,0 | 23:16, 7:0 | U22, RP5, RP6, RP7, RP8, RP14, RP15, R380 | |
| > 1GB | XX00XX00 | 3,1 | 31:24, 15:8 | U24, RP1, RP2, RP3, RP4, RP16, RP17, R376 |
| 00XX00XX | 2,0 | 23:16, 7:0 | U23, RP1, RP2, RP3, RP4, RP16, RP17, R376 |
If a laptop has 1 GByte of memory, the interleave is set to 512MB by default, and the following applies:
| Address | Error | Byte | Data bits | Location |
| < 512MB | XX00XX00 | 3,1 | 31:24, 15:8 | U21, RP5, RP6, RP7, RP8, RP14, RP15, R380 |
| 00XX00XX | 2,0 | 23:16, 7:0 | U22, RP5, RP6, RP7, RP8, RP14, RP15, R380 | |
| > 512MB | XX00XX00 | 3,1 | 31:24, 15:8 | U24, RP1, RP2, RP3, RP4, RP16, RP17, R376 |
| 00XX00XX | 2,0 | 23:16, 7:0 | U23, RP1, RP2, RP3, RP4, RP16, RP17, R376 |
