Geode instruction set
Generally speaking, the Geode processor is like the original Athlon. It supports the i686 (Pentium Pro) instruction set, MMX, the parts of SSE that do not involve SSE registers, 3DNow! Enhanced, a couple Geode-specific instructions and a few SSE2 instructions.
There are also numerous kernel-only instructions and MSRs for dealing with an extra debug mode, for directly loading and saving the normally-hidden segment state (base, limit, etc.) and so on.
Geode-specific 3DNow! instructions
- Opcode "0F 0F / 86" is "PFRCPV xr,xr/m64" or "PFRCPV Pq,Qq". It performs floating-point reciprocal approximation for a pair of 32-bit floats in an MMX register. It is like the PFRCP instruction, except that it operates on a pair of values.
- Opcode "0F 0F / 87" is "PFRSQRTV xr,xr/m64" or "PFRSQRTV Pq,Qq". It performs floating-point reciprocal square root approximation for a pair of 32-bit floats in an MMX register. It is like the PFRSQRT instruction, except that it operates on a pair of values.
useful "undocumented" instructions
- Opcode "F1" is "INT1", a 1-byte version of the "INT 1" ("CD 01") instruction. This instruction is also known as ICEBP, and is in fact available (but mostly undocumented) on all x86 processors since the 80386.
- Opcode "D6" is "SALC", documented as "SETALC" with an incorrect description. This instruction sets all bits of AL to the carry flag. As with INT1, this instruction is available on all processors.
- packed average of unsigned byte, a=(a+b+1)/2 for 8 bytes
- packed average of unsigned word, a=(a+b+1)/2 for 4 words
- cache-bypassing MMX store with byte mask (uses edi as destination)
- cache-bypassing MMX store
- extract word into integer register, copies any word from an MMX register into a regular register
- insert word, copies any word from memory or an integer register into an MMX register
- signed max() on MMX words
- unsigned max() on MMX bytes
- signed min() on MMX words
- unsigned min() on MMX bytes
- move byte mask (MSB of MMX bytes) to integer register
- packed multiply high unsigned word (useful for division)
- prefetch using NTA register
- prefetch using T0 register
- prefetch using T1 register
- prefetch using T2 register
- packed sum of absolute byte differences
- packed shuffle word
- store fence (see mfence)