XO1.5 DCONIRQ ECO
This describes a change to early prototypes of the XO-1.5 motherboard. It fixes an error in GPIO assignments made on the B2 (and earlier) prototypes. Boards without this ECO will not reliably detect a DCON interrupt.
This only applies to XO-1.5 B2 phase motherboards.
The problem is that SMBALRT# is synchronized by the RTC clock (32 KHz) before being used as an interrupt. The DCON interrupt pin is asserted for one line period, or roughly 15 uS, and is thus usually missed.
GPIO12 provides a general purpose input capable of generating an SCI/SMI, which isn't synchronized to the RTC clock, nor is it "owned" by ACPI.
One concern is that GPIO12 is used by the processor when PCIRST# is asserted to determine the FSB clocking rate. This requires a pullup to +3.3V. If for some reason the DCON were to assert DCONIRQ during that time,
- Run a wire between R123 (the pad that isn't connected to +3.3VSUS --- this part is located on the "top" side of the motherboard) and the pad of R264 that is connected to R263 (these are located on the bottom side of the motherboard).
This version is harder to do, but required if you are also going to perform the EC/Host Interrupt ECO.
- Run a wire between U17 (the DCON), pin 6 and the pad of R264 that is connected to R263. All components are located on the bottom side of the motherboard, where the processor and other chips are mounted.