XO1.75 A2 A3 Changes: Difference between revisions
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m (moved XO1.75 A2 B1 Changes to XO1.75 A2 A3 Changes: There will be an A3 version of 1.75 before we get to a B1) |
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* Remove Q16, and short pins 2 and 3 (marked I and O). |
* Remove Q16, and short pins 2 and 3 (marked I and O). |
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* Remove Q16, and short pins 2 and 3 (marked I and O). |
* Remove Q16, and short pins 2 and 3 (marked I and O). |
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::<font color="#c00">Q16 mentioned twice here, perhaps you mean Q21?</font> --[[User:Quozl|Quozl]] 22:34, 14 April 2011 (UTC) |
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==VMEM stability== |
==VMEM stability== |
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Revision as of 22:34, 14 April 2011
These are the changes planned for the XO-1.75 B1 prototype, from the A2 prototypes.
A2 Electrical Fixes
These changes fix problems in the A2 prototypes:
SD power
These correct a mistake in Embedded Controller pin assignments for the SD power control signals.
- Depopulate R335 and R345.
- Remove Q16, and short pins 2 and 3 (marked I and O).
- Remove Q16, and short pins 2 and 3 (marked I and O).
- Q16 mentioned twice here, perhaps you mean Q21? --Quozl 22:34, 14 April 2011 (UTC)
VMEM stability
This corrects an undercompensation of the +1.5V memory power supply, and also delays the turn-on of the memory termination power supply.
- Change PR49 to 22K.
- Change PR52 to 47K.
- Populate PC37 with 0.1 uF.
eMMC
- Populate R95 with 10K.
- Connect BOOT_DEV_SEL to CN21.10
- Use +3.3V_SD1 to power the eMMC instead of +3.3V_NAND
J2
The MISO and MOSI pins on J2 are swapped (the SOC GPIO map was wrong).
SPI_MISO should be connected to U10.2, J2.1, and U11.AD15 (GPIO43)
SPI_MOSI should be connected to U10.5 , J2.4, and U11.AE15 (GPIO44)
A2 Layout Fixes
- Bring GPIO04 (pin 5) to a user-probeable pad, for brick recovery purposes. (It may need to be grounded during EC flash reprogram.)