EC Register Settings: Difference between revisions

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[[Category:Firmware]]
[[Category:Hardware]]
[[Category:SoC Project]]
{{OLPC}}
{{draft}}


Current Embedded Controller register Settings



=OFW Dump=
Using [http://dev.laptop.org/~joel/ec-dump.fth ec-dump.fth] under OpenFirmware: ['''old dump''']

GPIOO fc00: 68 0 1e 0
GPIOE fc10: 7 d7 ff 1 b fd
GPIOD fc20: e 91 0 0 9 60
GPIOIN fc30: fe b7 f7 e ff 71 2b
GPIOPU fc40: 0 0 0 0 0 0
GPIOOD fc50: 0 80 0 0
GPIOIE fc60: 99 68 1e f f4 c0 34
GPIOM fc70: 1
KBC fc80: 60 43 0 ff ae f4 10
PWM fe00: 0 0 0 0 0 0 cf cf 0 80 80 0 ff ff
GPT fe50: f 0 0 43 0 fa 27 10 0 20
SPI fea0: 0 0 0 0 0 64 4 0 0 0 0 0 0 4 0 0
WDT fe80: 0 0 0 70 5a 7
LPC fe90: 2 30 3 80 a0 fd 0 80 0 62 0 0 0 82 c0 1d
PS2 fee0: 2f 0 21 76 1 af 2f
EC ff00: a0 0 f 50 3 80 0 0 8c f0 83 20 12 94 52 95 0 0 1f 11 0 b 3e 83 9 0 0 0 0 20 37 0
GPWUEN ff30: 10 0 0 0
GPWUPF ff40: 89 8 16 c
GPWUPS ff50: 0 8 0 0
GPWUEL ff60: 0 8 0 0

* EC dump Q2C25
GPIOO fc00: 68 0 1e 0
GPIOE fc10: 87 d7 fe 1 f bd
GPIOD fc20: e 95 1 0 1 60
GPIOIN fc30: fe bf f7 e ff 71 27
GPIOPU fc40: 0 0 0 0 0 0
GPIOOD fc50: 0 80 0 0
GPIOIE fc60: 19 68 1e f f4 c0 3c
GPIOM fc70: 1
KBC fc80: 60 43 0 ff ae f4 10
PWM fe00: 0 0 0 0 0 0 cf cf 0 80 80 0 ff ff
GPT fe50: f 0 0 43 0 fa 27 10 0 20
SPI fea0: 0 0 0 0 0 64 24 0 0 0 0 0 0 4 0 0
WDT fe80: 3 0 50 25 9f b
LPC fe90: 2 30 3 80 a0 fd 0 80 0 62 0 0 0 82 c0 1d
PS2 fee0: 2f 0 21 5a 1 af 2f
EC ff00: a0 0 f 50 3 80 0 0 8d f0 83 1 17 94 52 95 0 0 1f 11 2 3 3e 83 0 1f 0 0 0 20 37 0
GPWUEN ff30: 10 0 0 0
GPWUPF ff40: 9 49 fe d
GPWUPS ff50: 0 0 0 0
GPWUEL ff60: 0 0 0 0

*EC dump Q2C26

GPIOO fc00: 68 0 1e 0
GPIOE fc10: 7 d7 fe 1 b bd
GPIOD fc20: e 95 1 0 1 60
GPIOIN fc30: f6 bf f7 e ff 71 27
GPIOPU fc40: 0 0 0 0 0 0
GPIOOD fc50: 0 80 0 0
GPIOIE fc60: 99 68 1e f f4 c0 3c
GPIOM fc70: 1
KBC fc80: 60 43 0 ff ae f4 10
PWM fe00: 0 0 0 0 0 0 cf cf 0 80 80 0 ff ff
GPT fe50: f 0 0 43 0 fa 27 10 0 20
SPI fea0: 0 0 0 0 0 64 24 0 0 0 0 0 0 4 0 0
WDT fe80: 0 0 50 1e 4d 9
LPC fe90: 2 30 3 80 a0 fd 0 80 0 62 0 0 0 82 c0 1d
PS2 fee0: 2f 0 21 5a 1 af 2f
EC ff00: a0 0 f 50 3 80 0 0 8d f0 83 1 12 94 52 95 0 0 1f 11 2 3 3e 83 4 49 0 0 0 20 37 0
GPWUEN ff30: 10 0 0 0
GPWUPF ff40: 89 48 1e d
GPWUPS ff50: 0 8 0 0
GPWUEL ff60: 0 8 0 0

=Register settings=
==GPIO General Purpose IO (include ADC, DAC)==

===GPIOO===

'''Output Function Select'''

'''''1''' - Alt. output''

'''''0''' - GPO''

fc00: 68 0 1e 0

===GPIOE===

'''Output Enable'''

'''''1''' - Enable''

'''''0''' - Disable''

fc10: 7 d7 ff 1 b fd

===GPIOD===
'''Data Output'''

fc20: e 91 0 0 9 60

===GPIOIN===
'''Input Status'''

fc30: fe b7 f7 e ff 71 2b

===GPIOPU===
'''Pull Up Enable'''

fc40: 0 0 0 0 0 0

===GPIOOD===
'''Open Drain Enable'''

fc50: 0 80 0 0

===GPIOIE===
'''Input Enable'''

fc60: 99 68 1e f f4 c0 34

===GPIOM===
'''Misc'''

fc70: 1


==KBC Keyboard Controller==
fc80: 60 43 0 ff ae f4 10

===KBCCB===
'''KBC Command Byte'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>RSV</td></tr>
<tr><td>6</td> <td>1</td> <td>Scan Code Conversion</td></tr>
<tr><td>5</td> <td>1</td> <td>Auxiliary Device Disable</td></tr>
<tr><td>4</td> <td>0</td> <td>Keyboard Device Disable</td></tr>
<tr><td>3</td> <td>0</td> <td>Inhibit Override</td></tr>
<tr><td>2</td> <td>0</td> <td>System Flag</td></tr>
<tr><td>1</td> <td>0</td> <td>IRQ12 Enable</td></tr>
<tr><td>0</td> <td>0</td> <td>IRQ1 Enable</td></tr>
</table>


===KBCCFG===
'''KBC Configuration'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>Keyboard Lock Enable</td></tr>
<tr><td>6</td> <td>1</td> <td>Fast Gate A20 Control</td></tr>
<tr><td>5</td> <td>0</td> <td>RSV</td></tr>
<tr><td>4</td> <td>0</td> <td>RSV</td></tr>
<tr><td>3</td> <td>0</td> <td>Keyboard Lock</td></tr>
<tr><td>2</td> <td>0</td> <td>RSV</td></tr>
<tr><td>1</td> <td>1</td> <td>IBF Interrupt Enable</td></tr>
<tr><td>0</td> <td>1</td> <td>OBF Interrupt Enable</td></tr>
</table>


===KBCIF===
'''KBC Interrupt Flag Pending Flag'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7~3</td> <td>0</td> <td>RSV</td></tr>
<tr><td>2</td> <td>0</td> <td>KBC Firmware mode in processing flag. Write 1 to exit firmware mode</td></tr>
<tr><td>1</td> <td>0</td> <td>IBF Interrupt pending flag</td></tr>
<tr><td>0</td> <td>0</td> <td>OBF Interrupt pending flag</td></tr>
</table>

===KBCHWEN===
'''KBC Hardware Command Enable'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>1</td> <td>FEh: KB Reset command processed by hardware</td></tr>
<tr><td>6</td> <td>1</td> <td>E0h: read test input command processed by hardware</td></tr>
<tr><td>5</td> <td>1</td> <td>D3h: write AUX output buffer</td></tr>
<tr><td>4</td> <td>1</td> <td>D2h: write KB output buffer</td></tr>
<tr><td>3</td> <td>1</td> <td>D1h: write P2 command command processed by hardware</td></tr>
<tr><td>2</td> <td>1</td> <td>D0h: read P2 command processed by hardware</td></tr>
<tr><td>1</td> <td>1</td> <td>C0h: read P0 command processed by hardware</td></tr>
<tr><td>0</td> <td>1</td> <td>20h: read command byte processed by hardware</td></tr>
</table>


===KBCCMD===
'''KBC Command Buffer''' The data written to IO port 64h will be stored in this register

===KBCDAT===
'''KBC Data IO Buffer'''' Writing to this register will cause OBF (Output Buffer Full) to set. Host reads this port through IO port 60h.

===KBCSTS===
'''KBC Host Status'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>Parity Error</td></tr>
<tr><td>6</td> <td>0</td> <td>Timeout</td></tr>
<tr><td>5</td> <td>0</td> <td>Auxiliary Data Flag</td></tr>
<tr><td>4</td> <td>0</td> <td>Uninhibited</td></tr>
<tr><td>3</td> <td>1</td> <td>Address (A2)</td></tr>
<tr><td>2</td> <td>0</td> <td>System Flag</td></tr>
<tr><td>1</td> <td>0</td> <td>IBF</td></tr>
<tr><td>0</td> <td>0</td> <td>OBF</td></tr>
</table>

==PWM Pulse Width Modulation==
fe00: 0 0 0 0 0 0 cf cf 0 80 80 0 ff ff

===PWMCFG===
'''PWM Configuration'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7~6</td> <td>0</td> <td>PWM1 Clock source selection</td></tr>
<tr><td>5</td> <td>0</td> <td>RSV</td></tr>
<tr><td>4</td> <td>0</td> <td>PWM1 Enable</td></tr>
<tr><td>3~2</td> <td>0</td> <td>PWM0 Clock source selection</td></tr>
<tr><td>1</td> <td>0</td> <td>RSV</td></tr>
<tr><td>0</td> <td>0</td> <td>PWM0 Enable</td></tr>
</table>

===PWMHIGH0===
'''PWM0 High Period Length'''

0x00

===PWMCYCL0===
'''PWM0 Cycle Length'''

0x00

===PWMHIGH1===
'''PWM1 High Period Length'''

0x00

===PWMCYCL1===
'''PWM1 Cycle Length'''

0x00

===PWMCFG2===
'''PWM2 Configuration'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>PWM2 Enable</td></tr>
<tr><td>6</td> <td>0</td> <td>PWM prescaler clock select (0: peripheral clock, 1: 1Mhz clock)</td></tr>
<tr><td>5~0</td> <td>0</td> <td>6-bit prescaler for PWM by selected clock</td></tr>
</table>

===PWMCFG3===
'''PWM3 Configuration'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>1</td> <td>PWM3 Enable</td></tr>
<tr><td>6</td> <td>1</td> <td>PWM prescaler clock select (0: peripheral clock, 1: 1Mhz clock)</td></tr>
<tr><td>5~0</td> <td>1111</td> <td>6-bit prescaler for PWM by selected clock</td></tr>
</table>

===PWMCFG4===
'''PWM4 Configuration'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>1</td> <td>PWM4 Enable</td></tr>
<tr><td>6</td> <td>1</td> <td>PWM prescaler clock select (0: peripheral clock, 1: 1Mhz clock)</td></tr>
<tr><td>5~0</td> <td>1111</td> <td>6-bit prescaler for PWM by selected clock</td></tr>
</table>


===PWMHIGH2===
'''PWM2 High Period Length''' High byte

0x00

===PWMHIGH3===
'''PWM3 High Period Length''' High byte

0x80

===PWMHIGH4===
'''PWM4 High Period Length''' High byte

0x80

===PWMCYC2===
'''PWM2 Cycle Length''' High byte

0x00

===PWMCYC3===
'''PWM3 Cycle Length''' High byte

0xFF

===PWMCYC4===
'''PWM4 Cycle Length''' High byte

0xFF

==GPT General Purpose 16-bit timer==
fe50: f 0 0 43 0 fa 27 10 0 20

===GPTCFG===
'''GTP Configuration'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7~5</td> <td>0</td> <td>RSV</td></tr>
<tr><td>4</td> <td>0</td> <td>GPT Test mode - GPT base clock will be system lcok</td></tr>
<tr><td>3</td> <td>1</td> <td>Enable GPT3 counting and interrupt</td></tr>
<tr><td>2</td> <td>1</td> <td>Enable GPT2 counting and interrupt</td></tr>
<tr><td>1</td> <td>1</td> <td>Enable GPT1 counting and interrupt</td></tr>
<tr><td>0</td> <td>1</td> <td>Enable GPT0 counting and interrupt</td></tr>
</table>


===GPTPF===
'''GPT Pending Flag'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>Write 1 to start GPT3</td></tr>
<tr><td>6</td> <td>0</td> <td>Write 1 to start GPT2</td></tr>
<tr><td>5</td> <td>0</td> <td>Write 1 to start GPT1</td></tr>
<tr><td>4</td> <td>0</td> <td>Write 1 to start GPT0</td></tr>
<tr><td>3</td> <td>0</td> <td>GPT3 interrupt pending flag</td></tr>
<tr><td>2</td> <td>0</td> <td>GPT2 interrupt pending flag</td></tr>
<tr><td>1</td> <td>0</td> <td>GPT1 interrupt pending flag</td></tr>
<tr><td>0</td> <td>0</td> <td>GPT0 interrupt pending flag</td></tr>
</table>


===GPT0===
'''GPT0 Count Value''' Once timer has reached this level, interrupt will occur and timer will restart from zero.

0x00

===GPT1===
'''GPT1 Count Value'''

0x43

===GPT2H,L===
'''GPT2 Count Value'''

0x00fa

===GPT3H,L===
'''GPT3 Count Value'''

0x2710

==SPI==
fea0: 0 0 0 0 0 64 4 0 0 0 0 0 0 4 0 0

==Watchdog Timer==
WDT fe80: 0 0 0 70 5a 7

===WDTCFG===
'''WDT Configuration'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th> <th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>WDT Extended Bits Enable (0=20 bit timer)</td></tr>
<tr><td>6~3</td> <td>0000</td><td>Force disable/set test mode/unset test mode</td></tr>
<tr><td>2</td> <td>0</td> <td>WDT Clock Selection for testing (0=normal)</td></tr>
<tr><td>1</td> <td>0</td> <td>Enable WDT interrupt</td></tr>
<tr><td>0</td> <td>0</td> <td>WDT timer reset</td></tr>
</table>

===WDTPF===
'''WDT Pending Flag'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th> <th>Description</th></tr>
<tr><td>7~5</td> <td>0</td> <td>RSV</td></tr>
<tr><td>1</td> <td>0</td><td>If set, next WDT timeout event will cause WDT reset signal</td></tr>
<tr><td>0</td> <td>0</td> <td>WDT reset event pending</td></tr>
</table>

===WTDCNT===
'''WDT 8-bit Count Value'''
Once WDT reaches this value, interrupt will occur.

===WTD Testing Counter Value===
'''For testing WDT'''
fe83 19->12
fe84 11->04
fe85 03->00

==LPC Low Pin Count==
'''Low Pin Count / Firmware Hub'''
fe90: 2 30 3 80 a0 fd 0 80 0 62 0 0 0 82 c0 1d

==PS2==
'''PS2 Controller'''
fee0: 2f 0 21 76 1 af 2f

===PS2CFG===
'''PS2 Configuration'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>RSV</td></tr>
<tr><td>6</td> <td>0</td> <td>Enable PS2 port 2</td></tr>
<tr><td>5</td> <td>1</td> <td>Enable PS2 port 1</td></tr>
<tr><td>4</td> <td>0</td> <td>RSV</td></tr>
<tr><td>3</td> <td>1</td> <td>Enable interrupt of PS2 parity error</td></tr>
<tr><td>2</td> <td>1</td> <td>Enable interrupt of PS2 TX timeout</td></tr>
<tr><td>1</td> <td>1</td> <td>Enable interrupt of PS2 transmitted byte</td></tr>
<tr><td>0</td> <td>1</td> <td>Enable interrupt of PS2 received byte</td></tr>
</table>

===PS2PF===
'''PS2 Pending Flag'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>RSV</td></tr>
<tr><td>6</td> <td>0</td> <td>Received byte port is PS2 port 2</td></tr>
<tr><td>5</td> <td>0</td> <td>Received byte port is PS2 port 1</td></tr>
<tr><td>4</td> <td>0</td> <td>RSV</td></tr>
<tr><td>3</td> <td>0</td> <td>Interrupt pending flag of PS2 parity error</td></tr>
<tr><td>2</td> <td>0</td> <td>Interrupt pending flag of PS2 TX timeout</td></tr>
<tr><td>1</td> <td>0</td> <td>Interrupt pending flag of PS2 PS2 transmitted byte</td></tr>
<tr><td>0</td> <td>0</td> <td>Interrupt pending flag of PS2 received byte</td></tr>
</table>

===PS2CTRL===
'''PS2 Transmitter / Receiver Control'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>RSV</td></tr>
<tr><td>6</td> <td>0</td> <td>Transmit byte port is PS2 port 1</td></tr>
<tr><td>5</td> <td>1</td> <td>Transmit byte port is PS2 port 1</td></tr>
<tr><td>4</td> <td>0</td> <td>RSV</td></tr>
<tr><td>3</td> <td>0</td> <td>Force reset of PS2 transmitter state</td></tr>
<tr><td>2</td> <td>0</td> <td>Force reset of PS2 reciever state</td></tr>
<tr><td>1</td> <td>0</td> <td>Flag of PS2 RX timeout</td></tr>
<tr><td>0</td> <td>1</td> <td>Enable PS2 transmit data port - set to transmit byte over PS2DATA</td></tr>
</table>

===PS2DATA===
'''PS2 Data'''

Read to get data of recieved byte from a PS2 device.

Write to transmit to a PS2 device. Will clear previous state.

===PS2CFG2===
'''PS2 Configuration 2'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7~2</td> <td>0</td> <td>RSV</td></tr>
<tr><td>1</td> <td>0</td> <td>PS2 protocol waiting time enable</td></tr>
<tr><td>0</td> <td>1</td> <td>PS2CLK/PS2DAT input de-bounce enable (0: 1us, 1: 2us)</td></tr>
</table>

===PS2PINS===
'''PS2 pin input status'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>1</td> <td>RSV</td></tr>
<tr><td>6</td> <td>0</td> <td>PS2 port 2 clock</td></tr>
<tr><td>5</td> <td>1</td> <td>PS2 port 1 clock</td></tr>
<tr><td>4</td> <td>0</td> <td>RSV</td></tr>
<tr><td>3</td> <td>1</td> <td>RSV</td></tr>
<tr><td>2</td> <td>1</td> <td>PS2 port 2 data</td></tr>
<tr><td>1</td> <td>1</td> <td>PS2 port 1 data</td></tr>
<tr><td>0</td> <td>1</td> <td>RSV</td></tr>
</table>

===PS2PINO===

'''PS2 pin output status'''

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>RSV</td></tr>
<tr><td>6</td> <td>0</td> <td>PS2 port 2 clock</td></tr>
<tr><td>5</td> <td>1</td> <td>PS2 port 1 clock</td></tr>
<tr><td>4</td> <td>0</td> <td>RSV</td></tr>
<tr><td>3</td> <td>1</td> <td>RSV</td></tr>
<tr><td>2</td> <td>1</td> <td>PS2 port 2 data</td></tr>
<tr><td>1</td> <td>1</td> <td>PS2 port 1 data</td></tr>
<tr><td>0</td> <td>1</td> <td>RSV</td></tr>
</table>

==EC Embedded Controller (hardware EC Space)==
'''EC Registers'''
ff00: a0 0 f 50 3 80 0 0 8c f0 83 20 12 94 52 95 0 0 1f 11 0 b 3e 83 9 0 0 0 0 20 37 0

===ECHV===
'''EC Hardware Revision ID''' A0 (default)
* OFWDUMP same

===ECFV===
'''EC Firmware Revision ID''' 0 (default)
* OFWDUMP same

===ECHA===
'''EC High Address''' default (F)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7~4</td> <td>0</td> <td>foo</td></tr>
<tr><td>3-0</td> <td>1111</td> <td>High-byte address of 64Kbyte EC address base.</td></tr>
</table>

* OFWDUMP same

===SCICFG===
'''SCI Configuration''' default (90)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>Enable generation of SCI by standard EC commands (default enable)</td></tr>
<tr><td>6</td> <td>1</td> <td>Enable SCID port (Firmware generated SCI)</td></tr>
<tr><td>5</td> <td>0</td> <td>EC SCI pulse polarity (1 low active (default), 0 high active)</td></tr>
<tr><td>4</td> <td>1</td> <td>Enable EC SCI (set 1) from SCIIFx (default enabled)</td></tr>
<tr><td>3~0</td> <td>0</td> <td>SCI pluse width = SCIPW x 64us. if 0, pluse width is system clock</td></tr>
</table>

* OFWDUMP 50
**diff
***EC SCI pulse polarity low active
***disabled EC SCI

===ECCFG===
'''EC Configuration''' default (0)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>Enable EPB Fast Access</td></tr>
<tr><td>6</td> <td>0</td> <td>Test mode (Set to 0 for normal operation)</td></tr>
<tr><td>5</td> <td>0</td> <td>Enable hardware EC Read/Write command</td></tr>
<tr><td>4</td> <td>0</td> <td>Enable hardware EC Burst Enable/Disable command</td></tr>
<tr><td>3</td> <td>0</td> <td>Enable hardware EC Query command</td></tr>
<tr><td>2</td> <td>0</td> <td>Enable Extended IO port interrupt to 8051</td></tr>
<tr><td>1</td> <td>1</td> <td>IBF Interrupt Enable. also be the Firmware Mode Enable. This bit enables KBC to generate interrupt to the 8051 at the rising edge of IBF, when the KBC command being received will be bypassed to firmware for processing.</td></tr>
<tr><td>0</td> <td>1</td> <td>OBF Interrupt enable. This bit enables KBC to generate interrupt to the core processor at the falling edge of OBF.</td></tr>
</table>

* OFWDUMP 3
**diff
***

===SCIE0===
'''Enable extended 8051 Port0 interrupt to SCI''' default (0)

===SCIE1===
'''Enable extended 8051 Port1 interrupt to SCI''' default (0)

===SCIE3 ===
'''Enable extended 8051 Port3 interrupt to SCI''' default (0)

===SCIF0===
'''Flag for extended 8051 Port0 interrupt to SCI''' default (0)

===SCIF1===
'''Flag for extended 8051 Port1 interrupt to SCI''' default (0)

===SCIF3===
'''Flag for extended 8051 Port3 interrupt to SCI''' default (0)

===SCID===
'''EC SCI_ID Write port for 8051 firmware to generate SCI event''' default (0)

===PMUCFG===
'''PMU Control / Configuration''' default (2F)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>1</td> <td>Enable PLL enter low speed state in STOP mode</td></tr>
<tr><td>6</td> <td>0</td> <td>Flash (SPI) Interface Clock Control</td></tr>
<tr><td>5</td> <td>0</td> <td>Enable PLL to generate 32.768Mhz</td></tr>
<tr><td>4</td> <td>1</td> <td>Enable PLL enter low power state in STOP mode</td></tr>
<tr><td>3~2</td> <td>01</td> <td>8051/Peripherals Normal Run Clock Selection
10: 22/8 MHz<br />
01: 16/8 MHz<br />
00: 8/4 MHz (default) the SPI clock is 16Mhz in this setting.<br />
Clock rate is fixed in 2/1MHz when 8051 in IDE if CLKCFG.0 is set. The flash interface (SPI or ISA) is fixed at 32.768 Mhz or higher by CLCKCFG.6 setting.</td></tr>
<tr><td>1</td> <td>0</td> <td>Enable Peripheral Auto Slow Clock control to be 1Mhz</td></tr>
<tr><td>0</td> <td>0</td> <td>Enable 8051 IDLE mode slow clock control to be 1/2 Mhz</td></tr>
</table>

===CLKCFG===
'''Clock Configuration''' default (00)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td> Enable PLL enter low speed state in STOP mode.
Set PLL frequency control value to be PLLLOW in STOP mode.
The CLKCFG bit 4 should also be enabled for this option.
</td></tr>
<tr><td>6</td> <td>0</td> <td> Flash (SPI) Interface Clock Control
* 1: full speed (Internal clock is 66(+-%25) MHz )
* 0: half speed (default, ½ of supplied clock)
* SPI clock is 16MHz if CLKCFG set to 8 / 4 MHz.
* SPI clock is stopped when 8051 in IDLE if CLKCFG.0 is set.
</td></tr>
<tr><td>5</td> <td>0</td> <td> Enable PLL to generate a good 32.768MHz. (default reset PLL)
This bit should be set after PCICLK is stable.
</td></tr>
<tr><td>4</td> <td>0</td> <td>Enable PLL enter low power state in STOP mode</td></tr>
<tr><td>3-2</td> <td>0</td> <td> 8051 / Peripherals Normal Run Clock Selection.
* 10: 22 / 8 MHz
* 01: 16 / 8 MHz
* 00: 8 / 4 MHz (default) The SPI clock is 16MHz in this setting.
Clock rate is fixed in 2/1MHz when 8051 in IDLE if CLKCFG.0 is set.
The flash interface (SPI or ISA) is fixed in 32.768 MHz or higher by
CLKCFG.6 setting.
</td></tr>
<tr><td>1</td> <td>0</td> <td> Enable Peripheral Auto Slow Clock Control to be 1 MHz.
The Peripheral's clock will be 1 MHz when no host accessing.
</td></tr>
<tr><td>0</td> <td>0</td> <td> Enable 8051 IDLE Mode Slow Clock Control to be 2 / 1 MHz.
When 8051 enters IDLE state, the clock of 8051 and peripherals will changed
automatically to 2 / 1 MHz. And the flash interface clock will be stop if this bit
is set.
</td></tr>
</table>

===EXTIO===
'''EC Extended Write IO Data''' default (0)

===PLLCFG===
'''PLL Configuration''' default (70)

===RSV===
foo

===CLKCFG2===
'''Clock Configuration 2''' default (1F)

===PLLCFG2===
'''PLL Configuration 2''' default (11)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7-6</td> <td>0</td> <td> PLLINIT High Bits (PLLINITH)
High 2 bits of PLL frequency control initial value(PLLINIT).
Combine with FF0Fh to be 10 bits frequency control value.
</td></tr>
<tr><td>5</td> <td>0</td> <td>PLL Reference Selection
* 0: select PCI clock(LPC clock) as reference clock of PLL.(default)
* 1: select alternative clock source from GPIO02 Alt. input.
</td></tr>
<tr><td>4</td> <td>0</td> <td>PLL Source Clock Divider
* 0: Disable
* 1: Enable (default)
The PLL build-in a 1024(10-bit) divider for source clock.For PLL reference
clock is high speed, as PCICLK, the divider should be enabled. For PLL
reference clock is low speed, as 32KHz from GPIO02 Alt. Input, the divider
should be disabled.
</td></tr>
<tr><td>3~0</td> <td>0</td> <td> PLL Low Speed State Setting
As Enable PLL enter low speed state in STOP mode,
Use this value as PLL frequency control.
</td></tr>
</table>

===PXCFG===
'''8051 on-chip Control''' default (0)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7~2</td> <td>0</td> <td>RSV</td></tr>
<tr><td>1</td> <td>0</td> <td> Enable WDT timeout only reset 8051
* 1: WDT timeout event only resets 8051.
* 0: The WDT timeout event resets whole chip
(not including GPIO module)
</td></tr>
<tr><td>0</td> <td>0</td> <td>Reset 8051 and 8051 internal peripherals(8051 serial port, timer, interrupt controller) . After reset, the 8051 will restart from reset vector if this bit is reset
to '0'. Write '1' to reset 8051. Write '0' to restart 8051.
</td></tr>
</table>

===ADDAEN===
'''ADC/DAC Enable''' default (0)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>Select converting ADC channel 5 (Valid in A1 Version only)</td></tr>
<tr><td>6</td> <td>0</td> <td>Select converting ADC channel 4 (Valid in A1 Version only)</td></tr>
<tr><td>5-0</td> <td>0</td> <td>Enable ADC5~0</td></tr>
</table>

===PLLFRH===
'''PLL Frequency Register High Byte''' default (3E)

===PLLFRL===
'''PLL Frequency Register Low Byte''' default (83)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7~4</td> <td>0</td> <td>32MHz clock count 32.768KHz value[3:0]</td></tr>
<tr><td>3</td> <td>0</td> <td>Enable show PLL lock value in CHIP ID reg</td></tr>
<tr><td>2</td> <td>0</td> <td> Enable PLL logic from test mode clock for testing.

</td></tr>
<tr><td>1~0</td> <td>0</td> <td> Set PLL frequency count don't care bits
* 0: all comparing
* 1: don't care bit 1
* 2: don't care bit 1~0
* 3: don't care bit 2~0
</td></tr>
</table>

===ADCTRL===
'''ADC Control Register''' default (0)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7-5</td> <td>0</td> <td>RSV</td></tr>
<tr><td>4-2</td> <td>0</td> <td> Select converting ADC channel (ADC5~0)
NOTE: ONLY Channel 3~0 is valid in A0 and A1 version. All these three bit
need to set ZERO if channel 4 or 5 selected using ADDAEN.
</td></tr>
<tr><td>1</td> <td>0</td> <td>ADC test mode</td></tr>
<tr><td>0</td> <td>0</td> <td>Start (write 1 action ) ADC converter and Enable ADC converted interrupt</td></tr>
</table>

===ADCDAT===
'''ADC Data output port''' After ADC converted, the value is held here. default (0)

===ECIF===
'''EC Interrupt Pending Flag''' default (0)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7-3</td> <td>0</td> <td>RSV</td></tr>
<tr><td>2</td> <td>0</td> <td> EC firmware mode in processing flag
Exit EC firmware mode and re-enable hardware mode by writing 1
</td></tr>
<tr><td>1</td> <td>0</td> <td>IBF interrupt pending flag, as ECSTS IBF is set by host write</td></tr>
<tr><td>0</td> <td>0</td> <td>OBF interrupt pending flag, as ECSTS OBF is clear by host read ECDAT
0
</td></tr>
</table>

===ECDAT===
'''EC Data Port''' Window between host and EC default (0)

===ECCMD===
'''EC Command Port''' Stores the latest EC command from host. default (0)

===ECSTS===
'''EC Status port''' default (0)

<table border="1" cellpadding="2" cellspacing="0">
<tr><th>Bit</th> <th>State</th><th>Description</th></tr>
<tr><td>7</td> <td>0</td> <td>Free r/w bit for host interface</td></tr>
<tr><td>6</td> <td>0</td> <td>Free r/w bit for host interface</td></tr>
<tr><td>5</td> <td>0</td> <td>SCI pending flag</td></tr>
<tr><td>4</td> <td>0</td> <td>Burst Enable Status</td></tr>
<tr><td>3</td> <td>0</td> <td>
A2 (Command or Data Flag)
* =0, previous host write is Data
* =1, previous host write is Command
</td></tr>
<tr><td>2</td> <td>0</td> <td>RSV</td></tr>
<tr><td>1</td> <td>0</td> <td>IBF, write IBF = 1 to clear IBF</td></tr>
<tr><td>0</td> <td>0</td> <td>OBF, write port ECDAT will set OBF to 1. Write OBF = 1 to clear OBF</td></tr>
</table>

===PLLVAL===
Chip Part No. / PLL lock value (works if bit 3 of PLLFRL is enabled)

==GPWU (hardware EC Space)==
'''General Purpose Wake Up'''
GPWUEN ff30: 10 0 0 0
GPWUPF ff40: 89 8 16 c
GPWUPS ff50: 0 8 0 0
GPWUEL ff60: 0 8 0 0

<table border="1" cellpadding="2" cellspacing="0">
<tr><td>GPWU</td>
<td>00</td><td>01</td><td>02</td><td>03</td><td>04</td><td>05</td><td>06</td><td>07</td>
<td>08</td><td>09</td><td>10</td><td>11</td><td>12</td><td>13</td><td>14</td><td>15</td>
<td>16</td><td>17</td><td>18</td><td>19</td><td>20</td><td>21</td><td>22</td><td>23</td>
<td>24</td><td>25</td><td>26</td><td>27</td><td>28</td><td>29</td><td>30</td><td>31</td>
</tr>
<tr><td>Event Enable</td>
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
<tr><td>Event Pending Flag</td>
<td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td>
</tr>
<tr><td>Polarity Selection</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
<tr><td>Edge/Level Trigger Selection</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
</tr>
</table>
[[Category:EC]]

Revision as of 06:23, 17 April 2012

chrismartins.Leur expertise fait d'eux les meilleurs interlocuteurs. franklin marshall 6- Ne pas manger suffisamment de protéines Pour perdre du poids, mangez plus de protéines.

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