Hardware Power Domains

This is a working document summarizing some power-related aspects of the chips used in the OLPC system. Right now it is a barely-structured collection of notes gleaned from a read-through of the various chip specs, with an eye for stuff related to power management.

Please feel free to add information. Links to cited documents would be useful...

Geode Chip

The main way to save power is to execute the HLT instruction when appropriate.

AHCG (see the 5536 topic for what AHCG means) is enabled via GLD_MS_PM 1000.2004h (statistics and time slice ctrs), 4000.2004h (online GLIU logic), 2000.2004h (memory controller), A000.2004h (BLT engine), and 8000.2004h (display controller). Display controller has 4 different clocks.

There is a 200-clock delay from self-refresh exit to first read command. See MSR 2000.001a

Power mode sensitivity counters - MSR 2000.0020h

Video

• Flat panel power management around page 377 of Geode manual (VP offset 0x410)
• Suspend-on-Halt can be turned on and off by MSR 1210h
• SMIs can be turned off with MSR 1301h
• Real stamp and time stamp counters can count (or not) during suspend - MSR 1900h

5536 Companion Chip

• Clock domain list on page 63 of 33238f_cs5536_ds.pdf
• Power management overview on p 79
• More info on page 169

• CPU supports clock stop
• No support for optional ACPI Sleep state S2
• No support for ACPI CPU states C3 and CT

5536 hardware power states

• FO (Full On) - all clocks always running (state after reset)
• AHCG (Active Hardware Clock Gating) - hardware automatically stops/starts clocks transparently
• Suspend on Halt - ACPI G0/S0/C1
• Sleep - ACPI G1/S1/C2
• Auto-refresh - DRAM kept "warm" (support for ACPI G1/S3 state)

5536 Power domains

• Working Domain: Vcore and Vio
  • Includes everything not listed below
• Standby Domain: Vcore_vsb and Vio_vsb
  • GPIO[31:24]
  • GPIO input conditioning functions 6 and 7
  • GPIO power management events 6 and 7
  • MFGPT[7:6]
  • Power Management Controller (PMC) Standby Controller and its I/O (WORKING, WORK_AUX, RESET_OUT)
  • PMC Standby registers starting at PMS I/O Offset 30h.
• RTC Domain - Vbat
  • Real Time Clock (always on)

• WORKING output controls Working domain power to system memory
• WORK_AUX output controls Working domain power to everything else

System starts in Full On state. Switch to AHCG state via power management MSRs (section 6.18.1 page 526). Each functional block has such an MSR at xxxx.2004h.

5536 Power Management MSRs

• GLCP_GLD_MSR_PM 51700004 - enable AHCG
• There are 47 clocks that can be independently controlled on the 5536. Things like USB (13 different clocks), PCI, IDE, Audio, etc.

Other 5536 tests

The MSRs have several BISTs, for things like FPU internals, etc.

DCON Chip

TBD

CaFe Chip

Global register at offset 0x3004 can turn off individual module clocks to SD, NAND, and CC. Also, that register has a "ClkRun Enable Set/Clear" bit pair

SD Controller Section

In principle (i.e. if the simplified SD spec is fully implemented), it will be possible to gate the power to the SD card.

Camera Controller Section

The clock control register at offset 0x88 lets you turn off PIXCLK

Control 1 Register - offset 0x40 - has PWRDNEN to power down the controller.

The power to the external sensor is supposed to be controlled by a GPIO

NAND Controller Section

Assuming that the controller deasserts CE* after an access, the NAND FLASH chips will automatically enter a low-power standby state (10 uA typical).

Wireless Controller Chip

TBD

KB3700 Keyboard Controller Chip

• Sleep State - 8051 program counter stopped
• Deep Sleep State - all internal clocks stopped (~10 uA for 144-pin version)
• But resetting the keyboard controller hard-resets the system!
• Power consumption targets for 64-pin version: RUN: 12 mA, IDLE: 3 mA, STOP: 500 uA

Clock domains

• Flash - (16 MHz to 64 MHz)
• 8051/XBI - uses high clock (setting CLKCFG) 22~4 MHz (whatever that means)
• WDT - 32 kHz
• Other peripherals use low clock (CLKCFG), 8~2 MHz

CLKCFG register can dial down the clocks.

Power management test plan (work in progress)

Hardware Setup

• Measure input current with ammeter, or
• If possible, measure specific power domains with voltmeters across sense resistors.

TBD - determine whether such sense resistor test points are available.

C1 test

• Turn off unnecessary devices and disable most interrupts
• Wait for current to stabilize and record reading
• Setup RTC alarm to fire after N seconds
• Execute HLT instruction
• Record new current reading
• Verify that system wakes up after RTC alarm fires

TBD: do we need to test wakeup from other interrupt sources?

ACPI power states (reference)

This section is a brief summary of ACPI power states, for reference

Global states

• G0 - running
• G1 - suspended but system state is recoverable "quickly"
• G2 - off, requires reboot to start, but power supply is attached
• G3 - mechanical off, no wall power or main battery power (RTC battery possibly present)

System states

• G0/S0 - not sleeping
• G1/S1 - many clocks off, but state maintained inside devices
• G1/S3 - suspend to RAM - devices powered off, so their state must be saved in RAM (RAM must be powered)
• G1/S4 - suspend to disk (RAM not powered)
• G2/S5 - full reboot required. 32 kHz clock running.
• G3 - everything off, except optionally the RTC (mechanical off)

CPU states

• G0/S0/C0 - CPU actively executing instructions
• G0/S0/C1 - CPU halted (HLT), waiting for interrupt. Cache snoops working, so bus mastering is possible.
• G1/S1/C2 - Lowest CPU power state that maintains CPU internal context. No need for snooping because (per S1 rules) devices are inactive.
• G0/S0/CT - clock throttling (not supported by Geode)

Device states

• D0 (need description)
• D1 (need description)
• D2 (need description)