GPIO Map: Difference between revisions

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(Add GPIO map to help us correctly program the pins)
 
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|28 || PWR_BUT# || X || || Power button input || || || || X || X ||
|28 || PWR_BUT# || X || || Power button input || || || || X || X ||
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[[Category:Hardware]]

Revision as of 13:58, 10 January 2007

This map details the usage of each GPIO pin on the 5536. (Last updated January 09, 2007 for B1):

PIN Usage Input Output Notes OUTPUT_ENABLE OUT_AUX1 OUT_AUX2 INPUT_ENABLE IN_AUX1 INPUT_EVENT_ENABLE
1 AC_BEEP X Connected to PCSPK X X
2 GPIO2 X Reads memory strap X
3 VGA SCL - - EDID line - not needed for XO machine
4 VGA SDA - - EDID line - not needed for XO machine
5 DCONSTAT0 X DCON status pin (1 of 2) X
6 DCONSTAT1 X DCON status pin (2 of 2) X
7 DCONIRQ X DCON Interrupt PIN X X
8 UART1_TX X UART Transmit X X
9 UART1_RX X UART Receive X X
10 UNUSED - - Goes to test point
11 DCONLOAD X Output indicator for DCON X
12 DCONBLNK X DCON Signal X
13 SMI# X SMI# pin to the GX X
14 SMB_CLK - - SMBus clock X X X
15 SMB_DATA - - SMBus data X X X
16 LPC_AD0 - - Defaults to LPC - no GPIO control
17 LPC_AD1 - - Defaults to LPC - no GPIO control
18 LPC_AD2 - - Defaults to LPC - no GPIO control
19 LPC_AD3 - - Defaults to LPC - no GPIO control
20 LPC_DRQ_L - - Defaults to LPC - no GPIO control
21 LPC_SERIRQ - - Defaults to LPC - no GPIO control
22 LPC_FRAME_L - - Defaults to LPC - no GPIO control
24 WORK_AUX X Xontrols MAIN_ON (which controls VCORE_CPU) X X
25 - - - Unknown - line is SWI# goes into GPIO2 on the EC
26 UNUSED - - Goes to test point
27 - - - Unknown - line is SCI# goes into GPIO5/SCI# on the EC
28 PWR_BUT# X Power button input X X